Search - devider

[Other resource] LCD

Description: 富士通单片机MB902420系列The internal LCD-cotroller will be initialised (1/2 bias, 1/2 duty). The internal Resistor devider is used. Some different methods are shown, how segments can be swicthed on/off.
Platform: | Size: 181965 | Author: 叶良 | Hits:

[SCM] LCD

Description: 富士通单片机MB902420系列The internal LCD-cotroller will be initialised (1/2 bias, 1/2 duty). The internal Resistor devider is used. Some different methods are shown, how segments can be swicthed on/off.-Fujitsu MB902420 Series Singlechip The internal LCD-cotroller will be initialised (1/2 bias, 1/2 duty). The internal Resistor devider is used.Some different methods are shown, how segments can be swicthed on/off.
Platform: | Size: 181248 | Author: 叶良 | Hits:

[VHDL-FPGA-Verilog] devider

Description: a divider design based on verilog language
Platform: | Size: 2048 | Author: Xiao Yang | Hits:

[VHDL-FPGA-Verilog] vhdl-devider

Description: 基于vhdl的分频器设计，分频器在数字系统设计中应用频繁-VHDL-based design of the divider, divider in the digital system design applications frequently
Platform: | Size: 1024 | Author: tony | Hits:

[VHDL-FPGA-Verilog] clk_div

Description: Clock devider in VHDL code
Platform: | Size: 2048 | Author: Haitham | Hits:

[Software Engineering] VHDLsourcecode

Description: source code for counter, freq devider, traffic light, stepper motor, flipflop
Platform: | Size: 2048 | Author: ibnudahlan | Hits:

[VHDL-FPGA-Verilog] FPGA-DEVIDER

Description: 基于FPGA的小数分频器的实现频率合成技术是现代通讯系统的重要组成部分,他将一个高稳定和高准确度的基准频率,经过四则运算,产生同样稳定度和基准度的频率。-FPGA-based implementation of the fractional divider frequency synthesis technology is an important component of modern communications systems, he has a high stability and high accuracy reference frequency, after four operations, have the same degree of stability and the frequency of reference.
Platform: | Size: 66560 | Author: lishaohui | Hits:

[VHDL-FPGA-Verilog] decoderMulTs

Description: its a perfect pipeline devider.-its a perfect pipeline devider.
Platform: | Size: 24576 | Author: farshid | Hits:

[Other] devider

Description: It s a EDA devider,write with AHDL language.
Platform: | Size: 3072 | Author: kay | Hits:

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[Other resource] LCD

[SCM] LCD

[VHDL-FPGA-Verilog] devider

[VHDL-FPGA-Verilog] vhdl-devider

[VHDL-FPGA-Verilog] clk_div

[Software Engineering] VHDLsourcecode

[VHDL-FPGA-Verilog] FPGA-DEVIDER

[VHDL-FPGA-Verilog] decoderMulTs

[Other] devider

[VHDL-FPGA-Verilog] debouncer_vhdl

[VHDL-FPGA-Verilog] devider

[Energy industry] Section2

[Energy industry] Vdiv_1

[Other] divider fpga4student

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