Search - de2_default

[Embeded-SCM Develop] DE2_Default

Description: his design is the initial design when the board is powered-up. It increments a counter and displays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.-his design is the initial design when the bo ard is powered-up. It increments a counter and d isplays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.
Platform: | Size: 270233 | Author: 木易 | Hits:

[Other resource] DE2_Default

Description: DE2开发版的默认程序，verilog，里面对各个模块都进行了控制，而且程序非常规范，值得学习
Platform: | Size: 3140616 | Author: 张伟 | Hits:

[Embeded-SCM Develop] DE2_Default

Description: Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。
Platform: | Size: 275288 | Author: wang | Hits:

[Other resource] DE2_Default

Description: 这是一个基于DE2平台的工程，适合于初学者学习DE2开发平台的很好的工程，是用Verilog语言编写的
Platform: | Size: 146434 | Author: wang | Hits:

[Other resource] DE2_Default

Description: 基于DE2开发板的VGA显示模块，仅供大家参考
Platform: | Size: 269927 | Author: lq | Hits:

[Embeded-SCM Develop] DE2_Default

Description: his design is the initial design when the board is powered-up. It increments a counter and displays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.-his design is the initial design when the bo ard is powered-up. It increments a counter and d isplays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.
Platform: | Size: 270336 | Author: 木易 | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: DE2开发版的默认程序，verilog，里面对各个模块都进行了控制，而且程序非常规范，值得学习-DE2 development version of the default proceedings, verilog, inside of each module have been controlled and standardized procedures, it is worth learning
Platform: | Size: 3140608 | Author: 张伟 | Hits:

[Embeded-SCM Develop] DE2_Default

Description: Verilog代码，适合于初学者进行学习，是基于DE2平台的代码。-Verilog code, suitable for beginners to learn, is based on the DE2 platform code.
Platform: | Size: 275456 | Author: wang | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: 这是一个基于DE2平台的工程，适合于初学者学习DE2开发平台的很好的工程，是用Verilog语言编写的-This is a project based on the DE2 platform, suitable for beginners to learn DE2 development platform works well, is to use Verilog language
Platform: | Size: 146432 | Author: wang | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: 基于DE2开发板的VGA显示模块，仅供大家参考-DE2 development board based on the VGA display module, for your reference
Platform: | Size: 269312 | Author: lq | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: altera DE2自带的默认检测程序可以测试所有器件-altera DE2 own default testing procedures to test all devices
Platform: | Size: 4096 | Author: chxinrui | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: 自己编程的采用verilog语言实现的关于altera的DE2-70开发板的一个实用程序，实现的是自动售货机的找零功能-Own programming language used on the altera verilog the DE2-70 development board of a utility, to achieve the change for vending machines function
Platform: | Size: 8800256 | Author: 舒念 | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: DE2开发板基本代码 DE2开发板基本代码 -basic
Platform: | Size: 3908608 | Author: 鲁金屏 | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: 延时一个时间通过QUARTUS环境编写VHDL代码-delay a time
Platform: | Size: 268288 | Author: fdsa | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: Altera DE2 demonstration design, lot of interesting verilog code for synthesis
Platform: | Size: 5107712 | Author: alzemiro | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: AUDIO_DAC VHDL PROGRAM FOR FPGA
Platform: | Size: 350208 | Author: Aleks | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: altera d2e default example
Platform: | Size: 484352 | Author: rivenz liendz | Hits:

[VHDL-FPGA-Verilog] DE2_Default

Description: 基于altera公司EP2C35672C6的DE2板子的光盘中的自带文件。-Based on the DE2 board altera company EP2C35672C6 CD in its own file.
Platform: | Size: 273408 | Author: 毛孩子 | Hits:

[Other] DE2_Default

Description: DE2开发板 verilog语言描述 Quartus II环境-DE2 development board verilog language to describe
Platform: | Size: 4096 | Author: ynchu | Hits:

[Other] DE2_Default

Description: altera DE2 board config files ...do give it a try
Platform: | Size: 350208 | Author: imranity | Hits:

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[Embeded-SCM Develop] DE2_Default

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[Embeded-SCM Develop] DE2_Default

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[Other resource] DE2_Default

[Embeded-SCM Develop] DE2_Default

[VHDL-FPGA-Verilog] DE2_Default

[Embeded-SCM Develop] DE2_Default

[VHDL-FPGA-Verilog] DE2_Default

[VHDL-FPGA-Verilog] DE2_Default

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[VHDL-FPGA-Verilog] DE2_Default

[VHDL-FPGA-Verilog] DE2_Default

[VHDL-FPGA-Verilog] DE2_Default

[VHDL-FPGA-Verilog] DE2_Default

[VHDL-FPGA-Verilog] DE2_Default

[VHDL-FPGA-Verilog] DE2_Default

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