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[Windows Developmig_23

Description: 利用ISE的core generator生成的存储器接口设计(MIG),包括example design和user design-ISE using the core generator to generate the memory interface design (MIG), including the example design and user design
Platform: | Size: 951296 | Author: 彭朋 | Hits:

[VHDL-FPGA-Verilogddr2_model

Description: 从软件中自动生成的ddr2代码,是DDR2必不可少的 -Ddr2 code ~
Platform: | Size: 16384 | Author: 徐翔 | Hits:

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