Search - ddfs vhdl

[Other resource] ddfs

Description: 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
Platform: | Size: 87754 | Author: 黎明 | Hits:

[Other resource] DDFS_1

Description: 主要介绍DDFS的主要结构，和它的实现方法还有源代码（VHDL）-introduces the main structure and the implementation methods have the source code (VHDL)
Platform: | Size: 3165 | Author: 李逵 | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 我自己用vhdl实现编的dds，能实现正弦波，方波，三角波。-my own use VHDL to achieve series dds, able sine, square, triangle wave.
Platform: | Size: 87040 | Author: 黎明 | Hits:

[Data structs] DDFS_1

Description: 主要介绍DDFS的主要结构，和它的实现方法还有源代码（VHDL）-introduces the main structure and the implementation methods have the source code (VHDL)
Platform: | Size: 3072 | Author: 李逵 | Hits:

Description: 文中给出了用VHDL实现三角波正弦波方波的代码, 可以在maxPLUX2上运行,-In this paper, using the VHDL-wave sine wave square wave triangle realize the code, you can run maxPLUX2,
Platform: | Size: 2048 | Author: qibinchuan | Hits:

[VHDL-FPGA-Verilog] FPGAddfs

Description: 基于FPGA的直接数字频率合成器的设计与实现.-FPGA-Based Direct Digital Frequency Synthesizer Design and Implementation.
Platform: | Size: 222208 | Author: 周真 | Hits:

[Software Engineering] pllddfs

Description: 一种基于锁相环的数字频率合成器的设计-Based on Phase-Locked Loop Digital Frequency Synthesizer Design
Platform: | Size: 111616 | Author: 周真 | Hits:

[VHDL-FPGA-Verilog] vhdlddfs

Description: 用VHDL设计直接数字频率合成器-VHDL design with direct digital frequency synthesizer
Platform: | Size: 190464 | Author: 周真 | Hits:

[Other] e

Description: 《EDA技术实用教程》实验选编专题一：计数分频器设计 4 专题二：存储器定制 7 实验一：快速乘法器电路设计 11 实验二：高速数字相关器设计 17 实验三：TLC5510高速A/D转换器控制 21 实验四：直接数字频率合成器（DDFS）设计 23 实验五：基于直接数字频率合成技术的任意波形发生器-" EDA technology practical course" Selected experimental one topic: the design count crossovers feature 4 2: 7 experiment a custom memory: Fast multiplier circuit design of 11 experiments II: the design of high-speed digital correlator 17, the experiment three: TLC5510 high-speed A/D converter control 21 of the experiment four: Direct Digital Frequency Synthesizer (DDFS) experimental design, 23 5: Based on Direct Digital Synthesis technology, arbitrary waveform generator
Platform: | Size: 2693120 | Author: 耿守浩 | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 基本FPGA的DDS信号发生器，可产生1-1MHZ任意频率的三角波，方波，锯齿波，正弦波-Basic FPGA-DDS signal generator, can produce 1-1MHZ arbitrary frequency triangle wave, square wave, sawtooth, sine wave
Platform: | Size: 1373184 | Author: 吴宏伟 | Hits:

[Software Engineering] fpgada0832

Description: 该波形发生器以单片机(MCS8031)为中心控制单元，由键盘输入模块、数码管显示模块、D/A波形发生模块dac0832、幅值调整模块组成。采用DDFS技术，先将要求的波形数据存储于EEPROM中，这样可以保证掉电以后波形数据不丢失。-The waveform generator to single-chip microcomputer (MCS8031) as the central control unit, by the keyboard input module, digital tube display module, D/A waveform occurred in module, the amplitude adjustment module. DDFS technology used, first the requirements of waveform data stored in EEPROM, so that after power-down waveform to ensure that data is not lost.
Platform: | Size: 172032 | Author: litong | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: vhdl编的dds函数发生器，完成sin(x)曲线的生成-vhdl function generator dds compiled to complete the sin (x) curve is generated
Platform: | Size: 91136 | Author: 王晓虎 | Hits:

[VHDL-FPGA-Verilog] ddfsdemo

Description: 直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.
Platform: | Size: 647168 | Author: 力文 | Hits:

[VHDL-FPGA-Verilog] ddfs

Description: 直接数字频率合成器，整个工程文件都在，仿真也有，直接就能用。-Direct digital frequency synthesizer, the entire project file are in the simulation is also directly be able to use.
Platform: | Size: 478208 | Author: 虎 | Hits:

[Other] mydds

Description: use vhdl to realize the ddfs
Platform: | Size: 662528 | Author: david gao | Hits:

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[Other resource] ddfs

[Other resource] DDFS_1

[VHDL-FPGA-Verilog] ddfs

[Data structs] DDFS_1

[VHDL-FPGA-Verilog] DDS234

[VHDL-FPGA-Verilog] FPGAddfs

[Software Engineering] pllddfs

[VHDL-FPGA-Verilog] vhdlddfs

[Other] e

[VHDL-FPGA-Verilog] ddfs

[Software Engineering] fpgada0832

[VHDL-FPGA-Verilog] ddfs

[VHDL-FPGA-Verilog] ddfsdemo

[VHDL-FPGA-Verilog] ddfs

[Other] mydds

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