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Description: cyclone上的PLL使用教材。好多人要得。-cyclone on the use of the PLL materials. Many people fine.
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Size: 554346 |
Author: cyj |
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Description: 1，原创 cyclone 2开发板，希望能对FPGA电子爱好者有一点设计帮助。
2，本PCB可以与开发者自己的PCB实现扩展。
3，注意接口已经提供5v,-5v，+3.3v,+1.2v输出。
4，带一个LED显示器，多路拨动开关，一个复位健。
5，晶振源兼容5种封装，其中一种是支持9v、5W高精度恒温晶振。
6，fpga内部2个PLL相互连接可以实现0－200MHz内任意频率输出。
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Size: 529477 |
Author: M |
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Description: cyclone上的PLL使用教材。好多人要得。-cyclone on the use of the PLL materials. Many people fine.
Platform: |
Size: 553984 |
Author: cyj |
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Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
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Size: 67584 |
Author: |
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Description: 1，原创 cyclone 2开发板，希望能对FPGA电子爱好者有一点设计帮助。
2，本PCB可以与开发者自己的PCB实现扩展。
3，注意接口已经提供5v,-5v，+3.3v,+1.2v输出。
4，带一个LED显示器，多路拨动开关，一个复位健。
5，晶振源兼容5种封装，其中一种是支持9v、5W高精度恒温晶振。
6，fpga内部2个PLL相互连接可以实现0－200MHz内任意频率输出。
Platform: |
Size: 529408 |
Author: M |
Hits:
Description: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。
PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。
-Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time.
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Size: 553984 |
Author: 裴雷 |
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Description: Cyclone II FPGA最小系统电路连接方式。包含JETAG配置和PLL配置-Minimum System Cyclone II FPGA circuit connections. Configuration and PLL configuration contains JETAG
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Size: 84992 |
Author: shenyiqun |
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Description: cyclone的pll应用，精确翻译，适合需要又不想看英文文献的同学。-cyclone the pll applications, accurate translation, suitable for students of English literature need not want to see.
Undo edits
Dictionary
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Size: 553984 |
Author: linhu |
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Description: cyclone器件的锁相环实现技术，包括锁相环的具体应用方法和使用细节，对于锁相环的学习者是个很好的教材。-implementation techniques, including details of the methods and use of the specific application of phase-locked loop the cyclone device s phase-locked loop, PLL learner is a good textbook.
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Size: 4175872 |
Author: 剑侠 |
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Description: PLL配置仿真实验
PLL，即锁相环。简单的理解，给PLL 一个时钟输入（一般是外部晶振时钟），
然后经过PLL 内部的处理以后，在PLL 的输出端口就可以得到一定范围的时钟频
率。其之所以应用广泛，因为从PLL 输出得到的时钟不仅仅从频率和相位上比较
稳定，而且其时钟网络延时也相比内部逻辑产生的分频时钟要小得多。-Altera FPGA Cyclone
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Size: 129024 |
Author: 相同 |
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