Search - crc in vhdl

[VHDL-FPGA-Verilog] crc_16

Description: 循环冗余校验，crc_16,主要运用在数字通信系统。用Verilog HDL编写。-Cyclic Redundancy Check, crc_16, mainly used in digital communications systems. Prepared with Verilog HDL.
Platform: | Size: 31744 | Author: 李鹏 | Hits:

[VHDL-FPGA-Verilog] CRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3072 | Author: 藏瑞 | Hits:

[Other] crc_pkg

Description: VHDL语言实现的CRC校验，函数形式，包括CRC4,CRC8,CRC16和CRC32-VHDL language to achieve the CRC checksum, function forms, including CRC4, CRC8, CRC16 and CRC32
Platform: | Size: 2048 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] pci_express_crc

Description: PCI express CRC rtl core for Fpga/asic Designer
Platform: | Size: 202752 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] vhdl_crc

Description: 在quartus中用VHDL语言开发的crc校验-Quartus VHDL language used in the development of CRC Checksum
Platform: | Size: 163840 | Author: 夏杰 | Hits:

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[Crack Hack] crc

Description: CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset-CRC code generator and calibration program Features: Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset
Platform: | Size: 5120 | Author: Alex | Hits:

[VHDL-FPGA-Verilog] crcm

Description: crc 校验，vhdl源码，经仿真能正常运行，供大家参考-CRC checksum, vhdl source, the simulation can be normal operation, for your reference
Platform: | Size: 1024 | Author: fangliang | Hits:

[Crack Hack] CRC

Description: 通过对于模2除法的研究可以得到如下方法： 1．把信息码后面加上p－1位的0，这个试验中p是6位，即在输入的信息码后面加上“00000”。把这个17位的被除数放入input中。 2．在得到被除数input之后，设计一个在被除数上移动的数据滑块变量d，把input中的最高位开始逐次复制给变量d。 3．如果d的最高位为1，由变量d和变量p做异或运算；如果d的最高位为0则不运算或者做多余的异或‘0’的运算。 4．把滑块变量d往后滑动一位。 5．循环步骤（3，4）11次。 6．执行步骤3。 7．得到余数c，把c转成信号输出。 -Through the 2-mode research division will be as follows: 1. Information code followed by the p-1-bit 0, this test p is 6, that is, the information in the input code after 00000. This 17 Add input in the dividend. 2. After receiving input dividend, dividend on the design of a mobile data slider variable d, the highest input in the beginning of successive copied to the variable d. 3. If the highest d for 1, by the variable d and variable p do XOR operations if d the highest computing to 0 or do not redundant XOR 0 arithmetic. 4. The slider sliding variable d next one. 5. Cycle of steps (3,4) 11. 6. Steps 3.7. Be more than a few c, the c into the output signal.
Platform: | Size: 6144 | Author: lijq | Hits:

[Software Engineering] CRC

Description: 　本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8 位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating different CRC polynomial and different degree of parallelism (eg, 8, 16, and 32-bit, etc.), with the current look-up table method has been used in comparison do not store more than a few tables, high-speed memory, reducing latency, and degree of parallelism can be increased to reduce the high-speed data-transmission system clock frequency of the CRC computation.
Platform: | Size: 144384 | Author: 黑月 | Hits:

[Embeded-SCM Develop] CRC

Description: CRC和线性码程序可能对初级学习有用希望能够好好利用-CRC
Platform: | Size: 30720 | Author: 黄金刚 | Hits:

[Software Engineering] stx_cookbook

Description: Altera公司高端FPGA高级综合指导手册，包括：算术运算单元，浮点处理技巧，数据编码格式转换，视频处理，仲裁逻辑，多路选择，存储逻辑，计数器，通信逻辑，循环冗余校验，随机和伪随机函数，加密和同步等编码风格和技巧；-advanced synthesis cookbook for Altera high-end FPGA(Stratix),incuding coding style and design tricks for arithmetic,floating points operation,tranlation and format convertion,vidio, arbitor, multiplexing, registers and memories,communication,CRC,random and pseudorandom functions,cryptography,synchronization,etc.
Platform: | Size: 962560 | Author: 刘易 | Hits:

[VHDL-FPGA-Verilog] crc

Description: 自己写的循环冗余校验，进行了仿真，整个工程都在！-Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
Platform: | Size: 436224 | Author: 虎 | Hits:

[VHDL-FPGA-Verilog] crc-gen

Description: CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
Platform: | Size: 60416 | Author: badfox | Hits:

[VHDL-FPGA-Verilog] CRC

Description: CRC循环校验码的生成。文件里是（40，32）的校验码生成电路，采用串行输入、串行输出的方式。-CRC checksum generation cycle. File is (40,32) of the check code generation circuit, the use of serial input, serial output mode.
Platform: | Size: 143360 | Author: 李雪茹 | Hits:

[VHDL-FPGA-Verilog] crc

Description: For implementing the CRC in verilog or VHDL
Platform: | Size: 100352 | Author: test | Hits:

[Crack Hack] PCK_CRC3_D4

Description: CRC校验码生存程序校验序列码生成多项式： X16+X13+X12+X11+X10+X8+X6+X5+X2+1 输入数据为16个字节（128位），输出16bit校验序列-CRC, the survival program check sequence code generator polynomial: X16+ X13+ X12+ X11+ X10+ X8+ X6+ X5+ X2+1 input data is 16 bytes (128 bits), output 16bit checksum sequence
Platform: | Size: 1024 | Author: weixin | Hits:

[VHDL-FPGA-Verilog] crc

Description: 本代码是CRC循环冗余校验实例，包含顶层原理图文件，十分直观-The CRC is cyclic redundancy check code examples, including the top-level schematic file, very intuitive
Platform: | Size: 449536 | Author: renjiale | Hits:

[VHDL-FPGA-Verilog] CRC-Parallel-Computation

Description: 用软件实现CRC校验码计算很难满足高速数据通信的要求，基于硬件的实现方法中，有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础，研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based implementations, there are classic serial algorithm LFSR, circuits and software algorithms derived from the other kinds of parallel computing. To the classic LFSR, circuit-based, study by the CRC byte parallel computing principles.
Platform: | Size: 205824 | Author: Geer | Hits:

[VHDL-FPGA-Verilog] CRC

Description: 4G-LTE标准中turbo编码所用到的CRC编码，绝对可用！(CRC encoding turbo encoding used in 4G-LTE standard)
Platform: | Size: 2048 | Author: 江41543434 | Hits:

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[VHDL-FPGA-Verilog] crc_16

[VHDL-FPGA-Verilog] CRC-Verilog

[Other] crc_pkg

[VHDL-FPGA-Verilog] pci_express_crc

[VHDL-FPGA-Verilog] vhdl_crc

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

[Crack Hack] crc

[VHDL-FPGA-Verilog] crcm

[Crack Hack] CRC

[Software Engineering] CRC

[Embeded-SCM Develop] CRC

[Software Engineering] stx_cookbook

[VHDL-FPGA-Verilog] crc

[VHDL-FPGA-Verilog] crc-gen

[VHDL-FPGA-Verilog] CRC

[VHDL-FPGA-Verilog] crc

[Crack Hack] PCK_CRC3_D4

[VHDL-FPGA-Verilog] crc

[VHDL-FPGA-Verilog] CRC-Parallel-Computation

[VHDL-FPGA-Verilog] CRC

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