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[Other resource] Cpu_model

Description: Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
Platform: | Size: 1530 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.
Platform: | Size: 44032 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] Cpu_model

Description: Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
Platform: | Size: 1024 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[VHDL-FPGA-Verilog] cpu86model

Description: 关于8086的软核fpga代码，可以直接再fpag的开发板上调试，好用而且是免费的-on the 8086 soft-core fpga code can then direct the development fpag board debugging, handy and free
Platform: | Size: 270336 | Author: 赵春生 | Hits:

[VHDL-FPGA-Verilog] SinglecycleCPU

Description: 用Verilog实现一个简单的单周期CPU，并运行Quicksort程序以验证正确性。-This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.
Platform: | Size: 26624 | Author: Matgek | Hits:

[VHDL-FPGA-Verilog] RISCcpu

Description: this verilog model of RISC CPU-this is verilog model of RISC CPU
Platform: | Size: 141312 | Author: Harshit B J | Hits:

[VHDL-FPGA-Verilog] RSIC_CPU2

Description: 这是一个用verilog编写的RSIC CPU模型，几个必要的模块都已经齐全，有兴趣的可以再完善更多的功能-This is a verilog written RSIC CPU model, several necessary modules are already complete, are interested in more features can be further improved
Platform: | Size: 237568 | Author: 宇龙 | Hits:

[VHDL-FPGA-Verilog] VeriRISC_CPU_Verilog

Description: Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.
Platform: | Size: 9216 | Author: 张昊溢 | Hits:

[VHDL-FPGA-Verilog] CPU_MODEL

Description: implementation of CPU model using verilog
Platform: | Size: 1024 | Author: kashif ali | Hits:

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