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[MiddleWare] counter

Description: 基于CPLD的计数器 实现光纤测距，包含与单片机的时序控制 Verilog 实现 通过仿真-CPLD-based counters realize optical ranging, single-chip microcomputer that contains timing control and realize the adoption of Verilog simulation
Platform: | Size: 2048 | Author: 强冰 | Hits:

[VHDL-FPGA-Verilog] coder_counter

Description: 增量式光电编码器计数器的FPGA实现程序,verilog3段式FSM,异步加载.-Incremental Optical Encoder counter program FPGA implementation, verilog3 struts FSM, asynchronous load.
Platform: | Size: 1024 | Author: | Hits:

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