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Description: 这是一个数字时钟的Verilog程序 仿真通过 能实现秒 分 时 计时-This is a digital clock Verilog simulation process can be achieved through the TDM time seconds
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Size: 354135 |
Author: liujl |
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Description:
Platform: |
Size: 354304 |
Author: liujl |
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Description: 利用单片机教学实验仪的MCU#3部分的数码管完成一个电子时钟的设计。-Teaching experiment instrument microchip MCU# 3 to complete a part of the digital electronic clock design.
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Size: 3072 |
Author: leo |
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Description: clk：基准时钟信号输入；
sec_narmal:周期为1s的信号输出；
sec_s:周期为0.5s的信号输出；
sec_m:周期为0.01s的信号输出；
sec_h:周期为0.0005s的信号输出；-clk: the reference clock signal input sec_narmal: The cycle of the signal output 1s sec_s: The cycle of the signal output 0.5s sec_m: cycle 0.01s signal output sec_h: The cycle of the signal output 0.0005s
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Size: 974848 |
Author: 田明 |
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