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Description: 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操
作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将
导致错误的行为，并且调试困难、花销很大。 在设计PLD/FPGA时通常采用几种时钟类型。时钟可
分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上
述四种时钟类型的任意组合。-without the expense of discrete logic, programmable logic, or a full-custom silicon device of any digital design, in order to successfully operate, reliable clock is very critical. The poor design of the clock, the limits of temperature, voltage or manufacturing process of the deviation would lead to wrong behavior, and debugging difficulties, costing much. The design PLD / FPGA usually use several types clock. The clock can be divided into the following four types : global clock, clock gating, multi-level logic clock and volatility clock. Multi-clock system to include the above four types of arbitrary clock portfolio.
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Size: 402195 |
Author: 与言 |
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Description: FPGA时钟分析，包括门控时钟与时钟偏仪分析，逻辑设计时钟分析，毛刺分析．-FPGA clock analysis, including clock gating and clock partial analysis, logic design clock analysis, Burr analysis.
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Size: 631033 |
Author: 罗辉 |
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Description: Clock gating logic for LEON3 processor.
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Size: 114700 |
Author: 岳昆 |
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Description: 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操
作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将
导致错误的行为，并且调试困难、花销很大。 在设计PLD/FPGA时通常采用几种时钟类型。时钟可
分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上
述四种时钟类型的任意组合。-without the expense of discrete logic, programmable logic, or a full-custom silicon device of any digital design, in order to successfully operate, reliable clock is very critical. The poor design of the clock, the limits of temperature, voltage or manufacturing process of the deviation would lead to wrong behavior, and debugging difficulties, costing much. The design PLD/FPGA usually use several types clock. The clock can be divided into the following four types : global clock, clock gating, multi-level logic clock and volatility clock. Multi-clock system to include the above four types of arbitrary clock portfolio.
Platform: |
Size: 402432 |
Author: 与言 |
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Description: FPGA时钟分析，包括门控时钟与时钟偏仪分析，逻辑设计时钟分析，毛刺分析．-FPGA clock analysis, including clock gating and clock partial analysis, logic design clock analysis, Burr analysis.
Platform: |
Size: 630784 |
Author: 罗辉 |
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Description: Clock gating logic for LEON3 processor.
Platform: |
Size: 114688 |
Author: 岳昆 |
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Description: 本文重点详细讲述了gate clock的用法和设计-In this paper, the focus of a detailed account of the gate clock usage and design
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Size: 30720 |
Author: 子墨 |
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Description: 门控时钟与时钟偏移分析,也是时钟的问题，集中先发一下-Clock gating and clock skew analysis, is also the issue of clock
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Size: 84992 |
Author: 黎德才 |
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Description: FPGA设计中几个基本问题的分析及解决
多时钟系统，时钟设计，时钟歪斜，门控时钟，毛刺信号及其消除，FPGA中的延时设计，FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of burr signal, FPGA design of the delay, FPGA design should pay attention to other issues
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Size: 48128 |
Author: 江凯 |
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Description: 逻辑设计时钟分析，毛刺问题探讨，门控时钟与时钟偏移分析-Clock logic design analysis, burr problems, clock gating and clock skew analysis
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Size: 630784 |
Author: dan |
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Description: 四位LED时钟显示程序
RB1-SW1秒设置 RB2-SW2分设置 RB3-SW3时设置
RB1--RB7接LED段码，RA0--RA3做选通
使用4M晶振TMR0滪分频为1：16 TMRO的循环时间为4.096MS 244次为一秒
用sec_nth计数-Four LED clock display program RB1-SW1 second sub-set RB2-SW2 set when setting RB3-SW3 RB1- RB7 access LED Segment, RA0- RA3 do Gating use TMR0 Yu 4M crystal frequency to the cycle time of 1:16 TMRO 4.096MS 244 times for one second with sec_nth count
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Size: 2048 |
Author: xiong |
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Description: 基于CC2530 功耗管理。CC2530有4个功耗模式-CC2530 use a different operating mode or power mode to allow low-power operation. Ultra-low power consumption by turning off the power supply module in order to avoid static power consumption as well as through the use of clock gating on and off to reduce dynamic power oscillator obtained.
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Size: 3072 |
Author: cheb |
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Description: DSP的SPI工作原理DSP，CPLD，74HC595（串入并出的移位器），共阳数码管。SPIMOSI和
SPICLK直接从DSPJIE接到了74HC595的SER和SRCLK，作为数据和时钟信
号的输入，SPICS由CPLD引出来控制74HC595的选通。-DSP SPI works DSP, the CPLD, 74HC595 (string in and out of the shifter), Yang digital tube. The SPICLK SPIMOSI and directly from the DSPJIE received 74HC595 SER and SRCLK of, as the input data and clock signals, SPICS cited by the CPLD control 74HC595 gating.
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Size: 1024 |
Author: 闻枫 |
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Description: 摘 要 介绍了VLIW密码微处理器的多种低功耗设计方法。根据CMOS电路的能耗机制，对VLIW密码微处理器进行功耗分析。针对分析结果，运用门控时钟、指令前缀压缩、存储器分块访问和操作数隔离等低功耗技术，对VLIW密码微处理器功耗进行优化。基于SMIC的65nm工艺库和功耗分析工具PTPX进行功耗分析，实验结果表明，本文采用的低功耗方法能够有效降低VLIW密码微处理器的功耗。-The summary of several low-power design method of the the VLIW password microprocessor. According to the mechanism of the energy consumption of the CMOS circuit, the the VLIW password microprocessor power analysis. For the results of the analysis, the use of clock gating, instruction prefix compression, memory sub block access and operand isolation low power technology, to optimize the the VLIW password microprocessor power consumption. Based on SMIC the 65nm process libraries and power analysis tools PTPX power analysis, experimental results show that low-power method used in this paper can effectively reduce the power consumption of VLIW password microprocessor.
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Size: 455680 |
Author: zhang |
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Description: 在FPGA里运用Verilog HDL编写实现门控时钟，而不产生毛刺-In the FPGA using Verilog HDL prepared to achieve clock gating, without glitches
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Size: 243712 |
Author: 姜敏敏 |
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Description: Leakage power dissipation becomes a dominant
component in operation power in nanometer devices. This paper
describes a design methodology to implement runtime power
gating in a fine-grained manner. We propose an approach to use
sleep signals that are not off-chip but are extracted locally within
the design. By utilizing enable signals in a gated clock design, we
automatically partition the design into domains. We then choose
the domains that will achieve the gain in energy savings by
considering dynamic energy overhead due to turning on/off power
switches.
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Size: 276480 |
Author: muthupandy |
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Description: clock gating document.
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Size: 130048 |
Author: Yashwanth |
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Description: btc cg clock gating default for Linux v2.13.6.
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Size: 10240 |
Author: |
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Description: struct clk_branch - gating clock with status bit and dynamic hardware gating.
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Size: 2048 |
Author: ksdangyu |
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