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[Other resource] CAN协议控制器的Verilog实现

Description: 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
Platform: | Size: 39048 | Author: wl | Hits:

[Other Embeded program] CAN协议控制器的Verilog实现

Description: 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
Platform: | Size: 38912 | Author: wl | Hits:

[VHDL-FPGA-Verilog] fpga(CAN)

Description:
Platform: | Size: 865280 | Author: 刘立 | Hits:

[MPI] controller

Description: MIPS处理器的控制verilog代码，可综合，可仿真，属硬件描述语言，集成电路设计代码-MIPS control processor Verilog code can be integrated to simulation, a hardware description language, integrated circuit design code
Platform: | Size: 1024 | Author: 陈丰 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mem_ctrl.tar

Description: verilog 写的 memory controller ，可以控制SDRAM SRAM NOR -written in Verilog memory controller, can control SDRAM SRAM NOR
Platform: | Size: 331776 | Author: youjia | Hits:

[VHDL-FPGA-Verilog] ac97_verilog_sourcecode

Description: AC97芯片的verilog实现，有兴趣可以研究下。verilog是一种硬件开发语言，语法与c类似。与VHDL并列为IC开发两大编程语言-AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two
Platform: | Size: 124928 | Author: 小步 | Hits:

[VHDL-FPGA-Verilog] can_rtl_verilog.tar

Description: can控制器的verilog语言实现 （还要更多的说明语言了吗？我不知道该写什么了）-controller can realize the Verilog language (even more language it? I do not know what the writing)
Platform: | Size: 34816 | Author: 郑国栋 | Hits:

[Other] ref-sdr-sdram-verilog

Description: sdram控制器的开发程序，还有文档，可以参考以下-SDRAM controller development process, there is a document, you can refer to the following
Platform: | Size: 776192 | Author: 王鹏 | Hits:

[VHDL-FPGA-Verilog] display_control

Description: 一个LCD控制器的verilog源代码，可以方便的控制TFT LCD！-An LCD controller Verilog source code, can easily control TFT LCD!
Platform: | Size: 2048 | Author: shi | Hits:

[VHDL-FPGA-Verilog] can.tar

Description: can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
Platform: | Size: 54272 | Author: yu | Hits:

[VHDL-FPGA-Verilog] CAN_IP

Description: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Platform: | Size: 61440 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] can_verilog_source

Description: verilog code for can controller
Platform: | Size: 47104 | Author: subha | Hits:

[VHDL-FPGA-Verilog] design-of-CAN-based-on-VHDL

Description: 基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性-Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness
Platform: | Size: 2615296 | Author: chen xinwei | Hits:

[VHDL-FPGA-Verilog] USB

Description: USB控制器的VERILOG工程文件，工程为ISE的，可以编译通过，压箱底的东西了-USB controller VERILOG project file, works for the ISE, you can compile, pressure bottom of things
Platform: | Size: 156672 | Author: mike | Hits:

[VHDL-FPGA-Verilog] verilog-CAN-Controler

Description: 使用verilog语言实现的CAN控制器代码。-Use the CAN controller verilog language code.
Platform: | Size: 45056 | Author: 张秋光 | Hits:

[Program doc] Verilog-CAN-controler

Description: verilog hdl 语 言 实 现 的 CAN 控 制 器-CAN controller verilog hdl language
Platform: | Size: 2629632 | Author: 张磊 | Hits:

[Other] CAN(OpenCores)

Description: CAN控制器源码 Verilog-CAN controller source Verilog
Platform: | Size: 5863424 | Author: wang | Hits:

[Other] CAN--Verilog-code

Description: can协议转换控制器的Verilog代码，在Quartus软件上测试通过-The CAN protocol conversion controller Verilog code, through the test on Quartus software
Platform: | Size: 25600 | Author: 天蓝 | Hits:

[VHDL-FPGA-Verilog] sdram controller

Description: Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and the ability to randomly change column addresses on each clock cycle during a burst cycle. This reference design provides the user with a baseline SDRAM Controller design. The user may modify the design to meet specific design requirements. This document provides information on how this design operates and shows the user where changes can be made to support other functionality.
Platform: | Size: 8192 | Author: Robuster | Hits:

[VHDL-FPGA-Verilog] can_loopback_test

Description: 实现了can控制器Verilog编程使用niosII 开发平台(Can controller Verilog programming, the use of niosII development platform)
Platform: | Size: 14640128 | Author: 电中生 | Hits:
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