Description: can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases Platform: |
Size: 54272 |
Author:yu |
Hits:
Description: 数字频率计的设计可以分为测量计数和显示。其测量的基本原理是计算一定时间内待测信号的脉冲个数，这就要求由分频器产生标准闸门时间信号，计数器记录脉冲个数，由控制器对闸门信号进行选择，并对计数器使能断进行同步控制。控制器根据闸门信号确定最佳量程。-The design of digital frequency meter can be divided into measurement and display count. The basic principle of its measurement is calculated under test signal within a certain period of time the number of pulses, which have a standard requirement by the divider gate time signal pulse counter records the number of signals from the controller to choose the gates and counters to make off synchronous control can be carried out.Controller based on the gate signal to determine the optimum range. Platform: |
Size: 54272 |
Author:黄花 |
Hits:
Description: SDRAM控制器，以下是我用VHDL编写SDRAM Controller的全部资料。文档提供的SDRAM控制器能工作在125MHz，我在实际工程中用到了120MHz，但没有再往上做测试了-SDRAM controller, the following is my SDRAM Controller using VHDL to prepare all the information. Documentation provided by SDRAM controller can work in the 125MHz, I used in the actual works of 120MHz, but did not do test in 125MHz or more Platform: |
Size: 6203392 |
Author:何宗奎 |
Hits:
Description: 用VHDL编写实现的UART控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE. Platform: |
Size: 25600 |
Author:陈阳 |
Hits:
Description: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access. Platform: |
Size: 52224 |
Author:yanxp |
Hits:
Search - can controller test vhdl