Search - calculator in verilog

[VHDL-FPGA-Verilog] calculator

Description: 用VHDL编写的计算器，能实现简单的加减乘除四则运算
Platform: | Size: 21504 | Author: huyanlong | Hits:

[VHDL-FPGA-Verilog] alu181

Description: alu运算器vhdl代码，介绍了16中运算方法，可用于cpu的设计中-alu calculator VHDL code, introduction of 16 in computing methods, can be used for the design of cpu
Platform: | Size: 1024 | Author: 赵心 | Hits:

Description: 组成原理的大作业，写一个计算器，用verilog语言写的-The composition of the major principles of operation, write a calculator, using the language written in Verilog
Platform: | Size: 8943616 | Author: 陈江 | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制，显示在数码管LED8 上 D[7..0]是移位数据输入，由键2 和1 控制，显示在数码管2 和1 上 QB[7..0]是移位数据输出，显示在数码管6 和5 上:cn 是移位数据输出进位，显示在数码管7 上。-SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change, CLK its clock. By S0, S1, M to control the functions of the state of shift operations, with data loading, data maintenance, cycle shifted to right, into the digital cycle shifted to right, circle left, circle to the left into the digital functions. CLK is the clock pulse input through the key high 5 low M mode control, M = l-bit cyclic shift into when, controlled by the key 8 into the displacement of CO to allow input from 7 control keys: S Control Shift Mode 0-3, 6 button control from showing in the digital control LED8 on D [7 .. 0] is the shift data input from the keys 2 and 1 control, displayed in the digital tube 2 and 1 QB [7. .0] is the displacement data output, displayed on the LED 6 and 5: cn is a binary data output shift, showing 7 on in the digital co
Platform: | Size: 129024 | Author: 623902748 | Hits:

[VHDL-FPGA-Verilog] P1-2

Description: 用verilog实现的三位整数计算器，包括加减乘除法-implementation of calculator in VERILOG
Platform: | Size: 6144 | Author: 蓝玫 | Hits:

[VHDL-FPGA-Verilog] calculator

Description: 课设一个，又臭又长，是一个用verilog编写的计算器，对应革新科技的某个sopc开发平台，键盘会扫描，七段二极管会译码且是并行输出，上传的是整个工程，在该开发平台上基本正常，主程序段编写的较为幼稚，希望大家多多扔玉。注：主程序段预计做八位计算器，后来因为实验平台只有六个数码管无奈之下后两位没接，主程序中的ac有问题，在开发平台上没效果，压缩包里的图是主程序在quartus下的仿真图，开发环境是quartus，不知应选哪项。最后：初次上传欢迎指正 -Set up a class, but also smell and long, is a calculator written using verilog, corresponding to a sopc innovative science and technology development platform, the keyboard scan, seven-segment LED will be parallel decode and output, upload the entire project, In the normal development platform, the main program segment written in a more naive, I hope Members can throw jade. Note: The main program segment is expected to make eight calculators, and later because the experimental platform is only six digits after the two did not desperation then, the main program of the ac problems did not result in the development of platforms, compressed bag of Figure is the main program under the simulation diagram in quartus, development environment is quartus, do not know which of the election. Last: initial upload please correct me
Platform: | Size: 10809344 | Author: raven | Hits:

[VHDL-FPGA-Verilog] verilog_calculator

Description: 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
Platform: | Size: 16384 | Author: 刘涛 | Hits:

[VHDL-FPGA-Verilog] verilog_calculator

Description: 一个Verilog写的简易计算器。能进行二进制加减乘除运算，操作数通过按键输入并用数码管显示。当按下运算符号键后，计算器进行两个数的运算，数码管将结果显示出来。-A simple calculator written in Verilog. Binary addition and subtraction to multiplication and division, operating a few keystrokes and use digital display. When the press operator symbol key, calculator computation of two numbers, the digital control will display the results.
Platform: | Size: 228352 | Author: 张立 | Hits:

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[VHDL-FPGA-Verilog] calculator

[VHDL-FPGA-Verilog] alu181

[VHDL-FPGA-Verilog] verilog

[VHDL-FPGA-Verilog] shifter

[VHDL-FPGA-Verilog] P1-2

[VHDL-FPGA-Verilog] calculator

[VHDL-FPGA-Verilog] verilog_calculator

[VHDL-FPGA-Verilog] verilog_calculator

[VHDL-FPGA-Verilog] FINAL-371

[VHDL-FPGA-Verilog] calculator

[Software Engineering] src

[Disk Tools] cal_pipeline

[VHDL-FPGA-Verilog] synd

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