Search - cadence verilog

[Other resource] verilog

Description: 北大微电子学系于敦山老师的课件，介绍Verilog HDL、Cadence Verilog仿真器、可综合的Verilog HDL、设计举例、自动布局布线工具、Verilog的词汇约定等内容
Platform: | Size: 1550297 | Author: 唐进 | Hits:

[Other resource] Cadence_MEDICI

Description: 本手册共分为三部分：第一部分分为四章，分别介绍Cadence cdsSpice、virtuoso Editing、Diva和verilog。第二部分主要介绍MEDICI。第三部分是附录部分，是对前两章的一个补充,并简要的介绍了寄生元件提取语句的语法。
Platform: | Size: 16741413 | Author: zjh | Hits:

[Other resource] CadenceSimulationCourse

Description: Cadence Verilog Language and Simulation
Platform: | Size: 1183012 | Author: yuanxiaonan | Hits:

[VHDL-FPGA-Verilog] Open_Verilog_International_-_VERILOG-HDL_PLI_Refer

Description: pli的文档资料，是cadence出的，详细介绍了pli的使用方法-pli document, the cadence is introduced in detail the use pli
Platform: | Size: 421888 | Author: 王一民 | Hits:

Description: 北大微电子学系于敦山老师的课件，介绍Verilog HDL、Cadence Verilog仿真器、可综合的Verilog HDL、设计举例、自动布局布线工具、Verilog的词汇约定等内容-Department of Microelectronics, Peking University in the teacher s courseware mts on Verilog HDL, Cadence Verilog simulator can be integrated Verilog HDL, design, for example, automatic placement and routing tools, Verilog, etc. terms agreed
Platform: | Size: 1550336 | Author: 唐进 | Hits:

[Other] Cadence_MEDICI

Description: 本手册共分为三部分：第一部分分为四章，分别介绍Cadence cdsSpice、virtuoso Editing、Diva和verilog。第二部分主要介绍MEDICI。第三部分是附录部分，是对前两章的一个补充,并简要的介绍了寄生元件提取语句的语法。-This manual is divided into three parts: the first part is divided into four chapters, respectively, introduce Cadence cdsSpice, virtuoso Editing, Diva and verilog. Introduce the second part of the main MEDICI. The third part is the appendix of the first two chapters of a supplement to, and briefly introduce the components of the parasitic extraction statement grammar.
Platform: | Size: 16741376 | Author: zjh | Hits:

[Graph Drawing] CadenceSimulationCourse

Description: Cadence Verilog Language and Simulation
Platform: | Size: 1182720 | Author: yuanxiaonan | Hits:

[source in ebook] CadenceVerilogLanguageAndSimulation

Description: Cadence guide for verilog
Platform: | Size: 1208320 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] cadenceveriloglanguageandsimulationcourse

Description: cadence verilog lanaguage and simulation course
Platform: | Size: 1182720 | Author: navanee | Hits:

[VHDL-FPGA-Verilog] vlogref

Description: cadence verilog reference
Platform: | Size: 1324032 | Author: navanee | Hits:

[Other] CadenceVerilogLanguageAndSimulation

Description: A good reference for programming with Cadence Verilog
Platform: | Size: 1182720 | Author: Degia | Hits:

[VHDL-FPGA-Verilog] vani_tut

Description: A total of 52 files showing examples of shell scripting for Cadence NCSIM simulator, multiple single module + testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Distributed Algorithms Project.-A total of 52 files showing examples of shell scripting for Cadence NCSIM simulator, multiple single module+ testbench examples in verilog 1995/2001, a "Randomized Smoothing Networks" paper (doc)+ppt+verilog codes and test bench from my EE7700 Distributed Algorithms Project.
Platform: | Size: 270336 | Author: Stephen Bishop | Hits:

[VHDL-FPGA-Verilog] ncvlog

Description: Cadence NC-verilog user guide C adence NC-verilog user guide C adence NC-verilog user guide Cadence NC-verilog user guide-Cadence NC-verilog user guide Cadence NC-verilog user guide Cadence NC-verilog user guide Cadence NC-verilog user guide Cadence NC-verilog user guide Cadence NC-verilog user guide
Platform: | Size: 3240960 | Author: anwei2048 | Hits:

[VHDL-FPGA-Verilog] Introduction-to-Verilog

Description: Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, -Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, Verilog 1364
Platform: | Size: 191488 | Author: zhujizhen | Hits:

[Software Engineering] ncvlog

Description: Cadence公司的NC-Verilog® Simulator Help文档，内容很全面共1446页。-The Cadence® NC-Verilog® simulator is a Verilog digital logic simulator that combines the high-performance of native compiled code simulation with the accuracy, ﬂ exibility, and debugging capabilities of event-driven simulation.
Platform: | Size: 3313664 | Author: 高宇翔 | Hits:

[VHDL-FPGA-Verilog] verilog_a_modeling

Description: verilog-a 建模，在Cadence 中建立一个二级运放的VerilogA行为级模型，并进行建立时间等等仿真，以及对S/H电路的建模和仿真。 -verilog-a model in Cadence to create a secondary op amp VerilogA behavioral model and the simulation set-up time, etc., as well as S/H circuit modeling and simulation.
Platform: | Size: 2041856 | Author: 史培霖 | Hits:

[VHDL-FPGA-Verilog] System_Demons

Description: 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。 5.构造函数带参数的例子。 6.轮转仲裁的例子。 7.使用类摸板的例子。 8.如何在模块中包含子模块。 9.SystemC的Transaction级验证示例。 10.如何trace一个数组 11.SystemC中使用测试向量文件输入的例子。 12.SystemC采用UDP/TCP通信的例子。 13.Cadence的ncsc的例子。 -0 most simple SystemC program: hello, world. A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files. Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated. Delay (similar to verilog# time). In SystemC examples. 4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal. Constructor with parameters example. (6) examples of web arbitration. 7. The class Moban examples. 8 module contains a sub-module. 9.SystemC of Transaction-Level Verification example. 10 How to trace an array 11.SystemC use the example of the test vector file input. 12.SystemC using the example of the UDP/TCP communication. Examples of 13.Cadence the ncsc.
Platform: | Size: 532480 | Author: sdd | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list