Search - booth multiplier test

[Embeded-SCM Develop] 16bit_booth_multiplier_STG

Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] booth

Description: 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
Platform: | Size: 1024 | Author: lixiang | Hits:

[Embeded-SCM Develop] test_bench

Description: test bench for booth multiplier
Platform: | Size: 1024 | Author: judy | Hits:

[VHDL-FPGA-Verilog] multiplier.tar

Description: 用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过-Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass
Platform: | Size: 2048 | Author: 胡恩 | Hits:

[VHDL-FPGA-Verilog] booth-test-bench

Description: booth 乘法器的测试代码 booth testbench-booth multiplier test code booth testbench
Platform: | Size: 17408 | Author: jinglinde | Hits:

[VHDL-FPGA-Verilog] VHDL-test-codeBooth-multiplier

Description: VHDL实验代码：Booth乘法器，是一个基于VHDL语言开发的程序，非常的实用-VHDL test code: Booth multiplier, is a VHDL-based language development program, a very practical
Platform: | Size: 1024 | Author: Johonson | Hits:

[VHDL-FPGA-Verilog] mult-64bit-booth.txt

Description: 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
Platform: | Size: 94208 | Author: cunxi | Hits:

[Embeded-SCM Develop] test_bench

Description: test bench for booth multiplier
Platform: | Size: 1024 | Author: ectivehe | Hits:

[MPI] 32bit_multiply

Description: 包含32为乘法器的设计，用verilog语言实现，包括booth编码的实现，booth乘法器的实现，3_2压缩器的实现，4_2压缩器的实现，华伦斯树的实现，以及两个testbench文件用于测试。-Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.
Platform: | Size: 4096 | Author: DX | Hits:

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[Embeded-SCM Develop] 16bit_booth_multiplier_STG

[VHDL-FPGA-Verilog] booth

[Embeded-SCM Develop] test_bench

[VHDL-FPGA-Verilog] multiplier.tar

[VHDL-FPGA-Verilog] booth-test-bench

[VHDL-FPGA-Verilog] VHDL-test-codeBooth-multiplier

[VHDL-FPGA-Verilog] mult-64bit-booth.txt

[Embeded-SCM Develop] test_bench

[MPI] 32bit_multiply

[Software Engineering] boooth--MUL

[VHDL-FPGA-Verilog] booth_mult

[VHDL-FPGA-Verilog] 15x15mul

[ARM-PowerPC-ColdFire-MIPS] 16 bit signed number multiplier

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