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[
VHDL-FPGA-Verilog
]
xapp860
Description:
16通道DDR的LVDS接口（VHDL,Verilog and doc）-16-Channel, DDR LVDS Interface with Real-Time Window Monitoring
Platform:
|
Size:
650240
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Author:
wicky
|
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Search - bit_align_machine.vhd
Search - bit_align_machine.vhd