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[Other resource] code13

Description: PCM编码,通过输入编码电平与域值电平 生成8比特码-PCM coding, coding input level and value-Level Domain 8-bit code generation
Platform: | Size: 873 | Author: xlz | Hits:

[Communication] BPSK_Simulation_for_AWGN_Rayleigh_Channels

Description: BPSK SYSTEM SIMULATION We simulate the generation of random variables r0 and r1, which constitutes the input to detector.The detector output is compared with the binary transmitted sequence and an error counter is used to count the number of bit errors. -BPSK We simulate the gen Kearney of random variables r0 and r1. which constitutes the input to detector.The de tector output is compared with the binary trans mitted sequence and an error counter is used to c been the number of bit errors.
Platform: | Size: 3092 | Author: xiaoying | Hits:

[Com Port] simple_spi

Description: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Platform: | Size: 473099 | Author: Jack | Hits:

[Other] The C Programming Language-C语言详解英文版

Description: 这是一本讲解C语言的书，是英文编写，十分经典，是大部分公司的新职员入职之前必须要看的书籍之一，很多公司都以它作为培训教材，帮助你更快了解C语言的奥妙。 Contents l Preface l Preface to the first edition l Introduction 1. Chapter 1: A Tutorial Introduction 1. Getting Started 2. Variables and Arithmetic Expressions 3. The for statement 4. Symbolic Constants 5. Character Input and Output 1. File Copying 2. Character Counting 3. Line Counting 4. Word Counting 6. Arrays 7. Functions 8. Arguments - Call by Value 9. Character Arrays 10. External Variables and Scope 2. Chapter 2: Types, Operators and Expressions 1. Variable Names 2. Data Types and Sizes 3. Constants 4. Declarations 5. Arithmetic Operators 6. Relational and Logical Operators 7. Type Conversions 8. Increment and Decrement Operators 9. Bitwise Operators 10. Assignment Operators and Expressions 11. Conditional Expressions 12. Precedence and Order of Evaluation 3. Chapter 3: Control Flow 1. Statements and Blocks 2. If-Else 3. Else-If 4. Switch 5. Loops - While and For 6. Loops - Do-While 7. Break and Continue 8. Goto and labels 4. Chapter 4: Functions and Program Structure 1. Basics of Functions 2. Functions Returning Non-integers 3. External Variables 4. Scope Rules 5. Header Files 6. Static Variables 7. Register Variables 8. Block Structure 9. Initialization 10. Recursion 11. The C Preprocessor 1. File Inclusion 2. Macro Substitution 3. Conditional Inclusion 5. Chapter 5: Pointers and Arrays 1. Pointers and Addresses 2. Pointers and Function Arguments 3. Pointers and Arrays 4. Address Arithmetic 5. Character Pointers and Functions 6. Pointer Arrays; Pointers to Pointers 7. Multi-dimensional Arrays 8. Initialization of Pointer Arrays 9. Pointers vs. Multi-dimensional Arrays 10. Command-line Arguments 11. Pointers to Functions 12. Complicated Declarations 6. Chapter 6: Structures 1. Basics of Structures 2. Structures and Functions 3. Arrays of Structures 4. Pointers to Structures 5. Self-referential Structures 6. Table Lookup 7. Typedef 8. Unions 9. Bit-fields 7. Chapter 7: Input and Output 1. Standard Input and Output 2. Formatted Output - printf 3. Variable-length Argument Lists 4. Formatted Input - Scanf 5. File Access 6. Error Handling - Stderr and Exit 7. Line Input and Output 8. Miscellaneous Functions 1. String Operations 2. Character Class Testing and Conversion 3. Ungetc 4. Command Execution 5. Storage Management 6. Mathematical Functions 7. Random Number generation 8. Chapter 8: The UNIX System Interface 1. File Descriptors 2. Low Level I/O - Read and Write 3. Open, Creat, Close, Unlink 4. Random Access - Lseek 5. Example - An implementation of Fopen and Getc 6. Example - Listing Directories 7. Example - A Storage Allocator l Appendix A: Reference Manual 1. Introduction 2. Lexical Conventions 3. Syntax Notation 4. Meaning of Identifiers 5. Objects and Lvalues 6. Conversions 7. Expressions 8. Declarations 9. Statements 10. External Declarations 11. Scope and Linkage 12. Preprocessor 13. Grammar l Appendix B: Standard Library 1. Input and Output: 1. File Operations 2. Formatted Output 3. Formatted Input 4. Character Input and Output Functions 5. Direct Input and Output Functions 6. File Positioning Functions 7. Error Functions 2. Character Class Tests: 3. String Functions: 4. Mathematical Functions: 5. Utility Functions: 6. Diagnostics: 7. Variable Argument Lists: 8. Non-local Jumps: 9. Signals: 10. Date and Time Functions: 11. Implementation-defined Limits: and l Appendix C: Summary of Changes
Platform: | Size: 570630 | Author: wukoo0901@qq.com | Hits:

[matlab] code13

Description: PCM编码,通过输入编码电平与域值电平 生成8比特码-PCM coding, coding input level and value-Level Domain 8-bit code generation
Platform: | Size: 1024 | Author: xlz | Hits:

[Communication] BPSK_Simulation_for_AWGN_Rayleigh_Channels

Description: BPSK SYSTEM SIMULATION We simulate the generation of random variables r0 and r1, which constitutes the input to detector.The detector output is compared with the binary transmitted sequence and an error counter is used to count the number of bit errors. -BPSK We simulate the gen Kearney of random variables r0 and r1. which constitutes the input to detector.The de tector output is compared with the binary trans mitted sequence and an error counter is used to c been the number of bit errors.
Platform: | Size: 3072 | Author: xiaoying | Hits:

[Com Port] simple_spi

Description: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Platform: | Size: 473088 | Author: Jack | Hits:

[Other] 16bitCRC

Description: 16位CRC代码生成的小软件,可根据输入数据自动生成代码.非常方便.-16-bit CRC code generation small software, can be the basis of input data automatically generated code. Very convenient.
Platform: | Size: 164864 | Author: joewalker | Hits:

[TreeView] huffmantree

Description: Huffman code tree generation with a given input bit stirng
Platform: | Size: 2048 | Author: Archana | Hits:

[Other Riddle games] javaDaZi

Description: 打字游戏代码，用java写的，是JCreate编写的！游戏开始后，屏幕上方同时有四个数字分四列下落，每个数字由三位组成。玩家用键盘依次输入数字，如果输入的数字序列与某一列正在下落的数字三位全部相同，则给玩家加10分，该列数字消失，该列新产生数字并下落；如果输入的数字某一位不相同，则输入的数字序列全部作废，重新接收输入。某一列数字到达屏幕底部则游戏结束。 -Typing game code, written in java, is JCreate prepared! After the game starts, four top of the screen while the whereabouts of four digital points, each number consists of three components. Players enter the number in turn with the keyboard, if you enter a number sequence and number of the whereabouts of the three columns are all the same, then the player with 10 points, the series of numbers disappear, and the column number and whereabouts of the new generation If you enter a number bit different, then enter the number of sequences become void and re-receive input. A column of numbers to reach the bottom of the screen, the game ended.
Platform: | Size: 2048 | Author: 程望 | Hits:

[Delphi VCL] caisuzi1

Description: 单击“产生数字”或“开始新游 戏”后软件将随机产生一个无重 复 的4位数，使用者在对应输入框 内输入猜测的一组无重复4位数 ，单击“确认数字后”软件就会根 据这个数字给出几A几B，其中A 前面的数字表示位置正确的数的 个数，而B前的数字表示数字正 确而位置不对的数的个数。 如：正确答案为 5234，而 猜的人猜 5346，则是 1A2B，其 中有一个5的位置对了，记为1A ，而3和4这两个数字对了，而位 置没对，因此记为 2B，合起来 就是 1A2B。接着猜的人再根据 出题者的几A几B继续猜，直到 猜中（即 4A0B）为止。 注意事项:请在5 分钟之内完成,且 输入次数不得超过50 次不然 算失败 本产品纯属智利游戏,仅供娱乐-Click the "generation number " or "start a new tour Play "after the software will randomly generate a non-re- Complex 4-digit, the user input box in the corresponding Enter a group of non-repetition guess 4-digit , Click "confirm figures, " the software will root According to this figure shows a few A few B, where A The numbers indicate the correct position in front of the number of The number of digits before the number of B is The number of correct and incorrect number of locations. Such as: The correct answer is 5234, and Guess who guess 5346, it is 1A2B, its There is a 5 position of a, denoted 1A , While 3 and 4 of these two figures, while the bit Did not set right, so remember to 2B, together Is 1A2B. Then, according to people who guess A few questions were a few B keep guessing until Guess (that is, 4A0B) so far. Note: Please be completed within 5 minutes, and Enter no more than 50 times or else Operator failure This product is pure
Platform: | Size: 393216 | Author: 夏寂然 | Hits:

[VHDL-FPGA-Verilog] MYCRC

Description: 由于altera公司的CRC生成和校验模块不支持本系统使用的Cyclone IV E系列FPGA，因此本文独立设计了CRC模块。该模块的接口与altera公司的CRC模块接口基本一致，能够对16位输入的数据流进行CRC校验码生成和校验。本文采用CRC-CCITT生成项，其表达式为：X16+X12+X5+X0。本模块需要startp信号及endp信号指示数据传输的起始及结束。本模块采用状态机设计，对于数据头和数据尾分别由不同的状态来处理。在本模块中，使用了for循环，这会消耗较多的FPGA资源，但暂时任未发现其他改进的方法。-Because altera company' s CRC generation and checking modules do not support the use of the system Cyclone IV E series FPGA, so this independent design of the CRC module. The module' s interface with the CRC module interface altera' s basically the same, capable of 16-bit input data stream of CRC generation and checking. In this paper, CRC-CCITT generation entry, its expression is: X16+ X12+ X5+ X0. This module requires startp signal and endp signal indicating the start and end of data transmission. This module is a state machine design, and data for the end of the first data were handled by different states. In this module, use the for loop, which consumes more FPGA resources, but temporarily did not find any other ways to improve.
Platform: | Size: 4096 | Author: 陈建 | Hits:

[VHDL-FPGA-Verilog] mkjpeg.tar

Description: 用FPGA实现的JPEG编码器，可以直接使用，内含完成说明文档，经过验证无误。-• JPEG baseline encoding JPEG ITU-T T.81 | ISO/IEC 10918-1 • Standard JFIF header v 1.01 automatic generation • Color images only (3 components, RGB 24 or 16 bit, YUV input) • Two programmable Quantization tables • Hardcoded Huffman tables (luminance and chrominance) • 2.3 to 2.7 clock cycles per one input 24 bit pixel @ 50 Quality • OPB programming and data Host interface • 4:2:2 subsampling • Source code target independent, synthesizable RTL VHDL code • Detailed documentation
Platform: | Size: 21650432 | Author: | Hits:

[VHDL-FPGA-Verilog] simple_spi_latest.tar

Description: - 与摩托罗拉的SPI规格兼容 - 增强摩托罗拉MC68HC11串行外设接口 - 4项深读FIFO - 4项深写入FIFO - 中断后1代，2，3或4个转移字节 - 8位WISHBONE RevB.3经典界面 - 经营的输入时钟频率范围广泛 - 静态同步设计 - 完全可合成 - 130LUTs在Spartan-II，230在ACEX LCELLs的-- Compatible with Motorola s SPI specifications - Enhanced Motorola MC68HC11 Serial Peripheral Interface - 4 entries deep read FIFO - 4 entries deep write FIFO - Interrupt generation after 1, 2, 3, or 4 transfered bytes - 8 bit WISHBONE RevB.3 Classic interface - Operates from a wide range of input clock frequencies - Static synchronous design - Fully synthesizable - 130LUTs in a Spartan-II, 230 LCELLs in an ACEX
Platform: | Size: 575488 | Author: 张居林 | Hits:

[VHDL-FPGA-Verilog] basys2

Description: BASYS2 board,FPGA，实现M12序列的生成并加在低频二进制信号上（输入信号），之后实现了位同步提取。-BASYS2 board, FPGA, to achieve M12 sequence generation and added to the low-frequency binary signal (input signal), and then to achieve the bit synchronization extraction.
Platform: | Size: 137216 | Author: 尹晨光 | Hits:

[Communication] 140801-7575-ijet-ijens

Description: This paper proposes and analyses an efficient wireless telecommunication system with multiple antennas to the emission and reception MIMO (multiple input multiple output) with space diversity in an OFDM (Orthogonal Frequency Di vision Multiplex). The proposed system consists to add modified Alamouti encoder to the system OFDM to improve the performance of the destination by intimately collaborating with the antennas system. We analyse the performance of a DTT (Digital Terrestrial Television) broadcasting system that includes MIMO encoder, associate with OFDM techniques, which can improve the appreciation of the quality of transmission bit error rate (BER) in terms of (C/N) carrier-to-noise ratio. Different propagation channel models and configurations are considered for each diversity scheme. This study has been carried out in the context of MIMO -OFDM improvement for the next generation of Digital Terrestrial Television broadcasting systems.
Platform: | Size: 835584 | Author: Moyad | Hits:

[Other] 电子密码锁

Description: （1）主要任务是产生一个开锁信号，而开锁信号的形成条件是输入代码和已设置的密码相同。实现这种功能的电路构思有多种。比如：用2片8位数据锁存器或2片4位寄存器，一片存入开锁的代码，另一片存入密码，通过比较的方法判断，若二者相等，则形成开锁信号。 （2）在产生开锁信号后，要求输出声、光信号。其中音响的产生可以由开锁信号去触发一个音响电路。其中的光信号可以用开锁信号点亮LED指示灯。 （3）用按钮开关的第一个动作信号触发一个5S的定时器，若在5S内未将锁打开，则电路进入自锁状态，使之无法再打开，并由扬声器发出持续10秒的报警信号。((1) The main task is to generate a unlocking signal, and the formation condition of unlocking signal is that the input code and the set password are the same. There are many circuit ideas to realize this function. For example, if two 8-bit data latches or two 4-bit registers are used, one will store the unlocking code and the other will store the password. If they are equal, the unlocking signal will be formed. (2) After the unlocking signal is generated, it is required to output acoustic and optical signals. The generation of sound can trigger a sound circuit by unlocking signal. The light signal can be used to turn on the LED indicator with the unlocking signal. (3) Use the first action signal of the button switch to trigger a 5S timer. If the lock is not opened within 5S, the circuit will enter the self-locking state, so that it cannot be opened again, and the speaker will send an alarm signal lasting for 10 seconds.)
Platform: | Size: 377856 | Author: 刘贤瑜 | Hits:

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