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[Other resourcebaheyouxiji

Description: 一个用VHDL写的拔河游戏机,很好的。-one of the tug-of-war game was that good.
Platform: | Size: 5979 | Author: 徐凯波 | Hits:

[Other resourcebaheyouxiji

Description: 本程序利用VHDL语言实现拔河游戏机的功能
Platform: | Size: 755065 | Author: wangjiabin | Hits:

[Other Gamesbaheyouxiji

Description: 一个用VHDL写的拔河游戏机,很好的。-one of the tug-of-war game was that good.
Platform: | Size: 6144 | Author: 徐凯波 | Hits:

[VHDL-FPGA-Verilogbaheyouxiji

Description: 本程序利用VHDL语言实现拔河游戏机的功能-This procedure using VHDL language realize the function of tug-of-war game
Platform: | Size: 754688 | Author: wangjiabin | Hits:

[VHDL-FPGA-Verilogbaheyouxiji

Description: 用vhdl写的拔河游戏机代码,后缀名改为vhd即可-the code of baheyouxiji in vhdl
Platform: | Size: 6144 | Author: Henry | Hits:

[VHDL-FPGA-Verilogbaheyouxiji

Description: 拔河游戏机, 1、 设计一个能进行拔河游戏的电路。 2、 电路使用15个(或9个)发光二极管,开机后只有中间一个发亮,此即拔河的中心点。 3、 游戏双方各持一个按钮,迅速地、不断地按动,产生脉冲,谁按得快,亮点就向谁的方向移动,每按一次,亮点移动一次。 4、 亮点移到任一方终端二极管时,这一方就获胜,此时双方按钮均无作用,输出保持,只有复位后才使亮点恢复到中心。 5、 用数码管显示获胜者的盘数。教学提示: 1、 按钮信号即输入的脉冲信号,每按一次按钮都应能进行有效的计数。 2、 用可逆计数器的加、减计数输入端分别接受两路脉冲信号,可逆计数器原始输出状态为0000,经译码器输出,使中间一只二极管发亮。 3、 当计数器进行加法计数时,亮点向右移;进行减法计数时,亮点向左移。 4、 由一个控制电路指示谁胜谁负,当亮点移到任一方终端时,由控制电路产生一个信号,使计数器停止计数。 5、 将双方终端二极管“点亮”信号分别接两个计数器的“使能”端,当一方取胜时,相应的计数器进行一次计数,这样得到双方取胜次数的显示。 6、 设置一个“复位”按钮,使亮点回到中心,取胜计数器也要设置一个“复位”按钮,使之能清零。-1, design a circuit can be a tug of war game. 2, the circuit using the 15 (or 9) light-emitting diodes, only after the middle of a bright start, namely the center of a tug of war. 3, games, and each side holding a button, rapidly and constantly pressed to produce pulses, who according to fast, to whom the direction of bright spots on the move, every time, bright spots move once. 4, highlights the terminal diode when the move to either party, the party would win, this time the two sides had no role in the button, the output to maintain, and only reset after so bright to restore to the center. 5, digital tube display the number of the winner of the plate. Teaching tips: 1, buttons, signals that the input pulse signal, every time I press the button should be able to effectively count. 2, with reversible counter to add, subtract count input pulse signal, respectively to accept two-way, reversible, the original output of the counter state 0000, via decoder output, so that the middle of an L
Platform: | Size: 6144 | Author: kxsh | Hits:

[VHDL-FPGA-Verilogbaheyouxiji

Description: 用vhdl实验板子实现用led灯和按钮实现拔河游戏,通过按键快慢来决定灯的移动顺序,从而获胜-bahe game for led
Platform: | Size: 5965824 | Author: 快乐王 | Hits:

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