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[VHDL-FPGA-Verilogasync_uart

Description: 用verilog写的串口接收发送通信程序,已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
Platform: | Size: 2375680 | Author: 莫少宁 | Hits:

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