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Description: FPGA Verilog,双向端口的研究,比较全,由ASSIGN和ALWAYS模块组成,测试可用
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Size: 116406 |
Author: 鲍纯贝 |
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Description: FPGA Verilog,双向端口的研究,比较全,由ASSIGN和ALWAYS模块组成,测试可用-FPGA Verilog, bi-directional port studies comparing full-, and ALWAYS by ASSIGN modules, testing available
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Size: 115712 |
Author: 鲍纯贝 |
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Description: 以Lattice 器伴为例,描述如何在Verilog中指定管脚属饪功能(OE,RESET,IO CELL寄存器,双向IO,Latch IO,管脚Pin number, synthesis属性,输出电气规格...),状态机的使用,及其它Verilog进阶功能-With Lattice devices for example, it describes how to specify the pin function in Verilog (OE, RESET, IO CELL register, bi-directional IO, Latch IO, assign Pin number, synthesis properties, the output electrical specifications ...), using State Machine, and other advanced features of Verilog.
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Size: 126976 |
Author: Tim |
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Description: 利用Verilog HDL编写程序
利用assign语句实现加法器-Use Verilog HDL to write programs
Using the assign statement adder
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Size: 32768 |
Author: 姚远 |
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Description: 数码管设计：顶层为数码管的封装，用户可自己分配引脚。很实用的Verilog程序。-Digital design: the top of the digital package, the user can assign pin himself. Very practical Verilog program.
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Size: 1024 |
Author: 李飞 |
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Description: 用Verilog语言写的串口接收程序。通过串口助手发送数据，在数据输出端可以看到发送的数据。（需要自己分配FPGA引脚)-Verilog language used to write the serial receiver. Send data through the serial port assistant. It can be seen at the data output terminal of the data transmission. (Need to assign your own FPGA pin)
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Size: 1024 |
Author: 毛毛 |
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Description: he multiplication operator in Verilog is leads to what is called a context-determined expression. The width used for the arithmetic in a self-determined expression depends on the widths of the operands and the result. With assign c = a*b;. th
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Size: 10240 |
Author: Arnold2001 |
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