Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed. Platform: |
Size: 179551 |
Author:李中伟 |
Hits:
Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed. Platform: |
Size: 179200 |
Author:李中伟 |
Hits:
Description: 用VHDL语言描述的几个乘法器实例，如串行阵列乘法器等-VHDL language used to describe a few examples of multipliers, such as array multipliers, such as serial Platform: |
Size: 279552 |
Author:liuning |
Hits:
Description: 设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和
树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把
设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确 并对FPGA 实现的时序结果
进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm for BOO TH generate part of the plot, with a mixed array and a tree structure to achieve the sum of the partial product, while also using a fast rounding algorithm to improve the performance of multipliers. The design of the multiplier is divided into four lines, carried out a simulation using FPGA verification result is correct and FPGA timing to achieve the results analyzed. Platform: |
Size: 209920 |
Author:terry |
Hits:
Description: 4X4阵列乘法器，图可以按程序画看看，可以改进-4X4 array multiplier, see Figure can draw according to the procedure can improve Platform: |
Size: 128000 |
Author:abby |
Hits:
Description: this code is for 4*4 array multiplier in vhdl
it is vhd file that works very we-this code is for 4*4 array multiplier in vhdl
it is vhd file that works very well Platform: |
Size: 1024 |
Author:tejas |
Hits:
Description: multiplier in hdl, this is a very good pdf.this is Implementation of 4 bit array multiplier
using Verilog HDL and its testing on the
Spartan 2 FPGA. Platform: |
Size: 1459200 |
Author:payam |
Hits:
Description: 4位输入，8为输出列阵乘法器，列阵乘法器比之普通的移位乘法器具有更高的速度和更强的并行能力，且进一步升级十分方便。-4 input, 8 for the output array multiplier, array multiplier with higher speeds and greater parallelism than the ordinary shift multiplier, and further escalation is very convenient. Platform: |
Size: 781312 |
Author:李莫 |
Hits:
Search - array multiplier