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[VHDL-FPGA-Verilog] tiny16cpu_maxII

Description: 这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation
Platform: | Size: 240640 | Author: 李无志 | Hits:

[VHDL-FPGA-Verilog] color_bar

Description: 使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide.
Platform: | Size: 10240 | Author: 石坚 | Hits:

[Driver Develop] altera_93c66

Description: usb blaster 93c46烧写文件-usb blaster 93c46 programmer documentation
Platform: | Size: 1024 | Author: 大 | Hits:

[VHDL-FPGA-Verilog] ALTERA

Description: altera中文的器件选型手册，大家开发fpga采用altera的器件的话可以-altera Chinese manual device selection, the development of U.S. altera FPGA device used, then can
Platform: | Size: 706560 | Author: zhangxi | Hits:

[VHDL-FPGA-Verilog] DE2_USB_API

Description: Altera de2开发板提供的配套软件程序，用PC机上的应用软件来控制开发板外围器件，功能较全面-Altera de2 development board to provide the matching software program, used PC, application software to control the development board peripheral device, function more comprehensive
Platform: | Size: 9212928 | Author: 陈建 | Hits:

[VHDL-FPGA-Verilog] ug_alt_ufm

Description: ALTERA公司的MAXⅡ系列CPLD的内部flash使用教程，内容很详细，图文并茂，英文版。-ALTERA s MAX Ⅱ series CPLD to use the internal flash tutorial is very detailed, with illustrations in English.
Platform: | Size: 848896 | Author: blur | Hits:

[VHDL-FPGA-Verilog] altera_bootmethods

Description: altera u-boot niosii用户使用手册-altera u-boot niosii
Platform: | Size: 232448 | Author: sunlichao | Hits:

[VHDL-FPGA-Verilog] WallaceTreeImplementationInVHDL

Description: Wallace Tree Implementation in VHDL WT is one of the fastest way to implement multiplication of numbers in hardware design. (Optimized version) Tested in Altera 3.5u board by MonteCristo (H.U.T)
Platform: | Size: 6144 | Author: montecristo | Hits:

[VHDL-FPGA-Verilog] auk_udpipmac-v3.3.0.tar

Description: The Altera(R) UDP/IP function implements a hardware solution for the transmission and reception of UDP/IP encapsulated network traffic.
Platform: | Size: 742400 | Author: Seok Hoon Shin | Hits:

[VHDL-FPGA-Verilog] 6_USB_to_SDHC_Lab

Description: altera max10 USB demo，使用了phy，把开发板配置成U盘模式-altera max10 USB demo，using PHY device，design a U pan
Platform: | Size: 2219008 | Author: liuluren | Hits:

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