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Description: VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits-VHDL realize 128bitAES encryption algorithm LOW AREA realize cost-saving DATA FLOW for 8 bits
Platform: |
Size: 19456 |
Author: ZHUOHUI LI |
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Description: Full AES Simulation Code
Platform: |
Size: 1339392 |
Author: esl |
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Description: 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
Platform: |
Size: 87040 |
Author: dinxj |
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