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[VHDL-FPGA-Verilog] sbox

Description: verilog code for s-box generation for AES algorith
Platform: | Size: 1024 | Author: clock | Hits:

[Other] sbox-_proposed

Description: Implementation of AES S BOX using VHDL
Platform: | Size: 5120 | Author: Rajasekar | Hits:

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