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[Other] EMCRYPTCHIPFORFPGA

Description: 基于FPGA加密芯片设计论文（AES和DES算法）-FPGA-based encryption chip design thesis (AES and DES algorithm)
Platform: | Size: 1068032 | Author: David | Hits:

[Crack Hack] aes_encryption

Description: aes加密算法的VHDL代码实现，在FPGA芯片上调试过-aes encryption algorithm realize the VHDL code in FPGA chips upward tried
Platform: | Size: 6144 | Author: stym_001 | Hits:

[VHDL-FPGA-Verilog] AES_RTL

Description: 使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
Platform: | Size: 15360 | Author: 林夢魔 | Hits:

[Crack Hack] aes

Description: aes加密算法实现，经过FPGA验证的！-aes encryption algorithm, after FPGA validation!
Platform: | Size: 6144 | Author: guochao | Hits:

[VHDL-FPGA-Verilog] aes

Description: 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
Platform: | Size: 4096 | Author: wangrui | Hits:

[VHDL-FPGA-Verilog] aesencryption

Description: Aes encryption on Fpga
Platform: | Size: 4096 | Author: Ibrahim | Hits:

[Crack Hack] systemcaes_latest.tar

Description: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Platform: | Size: 83968 | Author: lxc | Hits:

[Crack Hack] AES_verilog

Description: AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
Platform: | Size: 79872 | Author: 刘蕊丽 | Hits:

[VHDL-FPGA-Verilog] aes_pipe_latest.tar

Description: implementation of AES encryption algorithm in vhdl/verilog
Platform: | Size: 188416 | Author: cooldude | Hits:

[VHDL-FPGA-Verilog] Encryption

Description: AES implementation in VHDL!! Wit LCD controls-AES implementation in VHDL!! Wit LCD controls!!
Platform: | Size: 17408 | Author: manishrb | Hits:

[Crack Hack] AES

Description: 详细描述了AES加密算法的过程及S盒变换，用VHDL语言描述，通俗易懂-AES encryption algorithm is described in detail the process and transform S box, with the VHDL language to describe, easy to understand
Platform: | Size: 559104 | Author: 韩颖 | Hits:

[Crack Hack] aes_imp

Description: AES CODE IN VHDL FOR ENCRYPTION AND DECRYPTION
Platform: | Size: 534528 | Author: dipika | Hits:

[File Format] AES-FPGA

Description: 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware uation.
Platform: | Size: 191488 | Author: Eric | Hits:

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