Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - aes Pipelined

Search list

[Windows Develop] file_encryption

Description: AES分组加密算法做的文件加解密演示, 采用多线程流水线方式对文件进行 读->加密/解密->写 操作.-AES block cipher algorithm for encryption and decryption so the paper presentations, the use of multi-threaded pipelined read on paper-> encryption/decryption-> write operation.
Platform: | Size: 18432 | Author: 周可 | Hits:

[Software Engineering] platforms

Description: A Pipelined Implementation of AES for Altera FPGA platforms.doc
Platform: | Size: 86016 | Author: Mohammad | Hits:

[VHDL-FPGA-Verilog] IC-149

Description: Top-down Implementation of Pipelined AES Cipher
Platform: | Size: 70656 | Author: Aisha | Hits:

[VHDL-FPGA-Verilog] AES

Description: Pipelined Implementation of AES Encryption Based on FPGA
Platform: | Size: 87040 | Author: rivercreamss | Hits:

[VHDL-FPGA-Verilog] aes_pipe

Description: 流水线AES加密VHDL代码，代码规范，值得参考- The VHDL code of Pipelined AES encryption
Platform: | Size: 12288 | Author: wughui | Hits:

[Industry research] aes_pipe_latest.tar

Description: VERILOG IMPLEMENTATION OF PIPELINED AES ALGORITHM
Platform: | Size: 186368 | Author: ANNIYAN | Hits:

[Software Engineering] ASE

Description: 可重构平台下AES算法的流水线性能优化，讲解比较到位，抛砖引玉可以-Reconfigurable platform performance optimization of pipelined AES algorithm, to explain more in place, so you can
Platform: | Size: 660480 | Author: orca | Hits:

[Crack Hack] AES-pipelined-architecture

Description: AES算法，采用FPGA实现，重点描述了流水线设计，使用才方法使加解密具有很高的吞吐率-An AES crypto chip using a high-speed parallel pipelined architecture
Platform: | Size: 356352 | Author: wucaidai | Hits:

[CA auth] aes-128_pipelined_encryption_latest.tar

Description: aes pipelined implementation
Platform: | Size: 519168 | Author: raji | Hits:

CodeBus www.codebus.net