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[Other resource] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25639 | Author: 79979 | Hits:

[VHDL-FPGA-Verilog] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25600 | Author: | Hits:

[VHDL-FPGA-Verilog] adpll

Description: 全数字锁相环 功能与74297相同 提供参数配置-All-digital phase-locked loop function and to provide parameters to configure the same 74,297
Platform: | Size: 2048 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] MinWinsockSpi

Description: verilog ADPLL file with testbench
Platform: | Size: 197632 | Author: xgh | Hits:

[VHDL-FPGA-Verilog] VCchuankou

Description: verilog ADPLL file with testbench
Platform: | Size: 206848 | Author: xgh | Hits:

[ARM-PowerPC-ColdFire-MIPS] ADPLL

Description: verilog语言编写的fpga的全数字锁相环ADPLL程序-Verilog language FPGA all digital phase-locked loop ADPLL program
Platform: | Size: 270336 | Author: 伊尔 | Hits:

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