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[Other resource] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25639 | Author: 79979 | Hits:

[Other resource] adpll

Description: 全数字锁相环 功能与74297相同 提供参数配置
Platform: | Size: 2056 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25600 | Author: | Hits:

[matlab] DPLL1lp

Description: 频带数字通信中，频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
Platform: | Size: 8192 | Author: rossi | Hits:

[VHDL-FPGA-Verilog] adpll

Description: 全数字锁相环 功能与74297相同 提供参数配置-All-digital phase-locked loop function and to provide parameters to configure the same 74,297
Platform: | Size: 2048 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] MinWinsockSpi

Description: verilog ADPLL file with testbench
Platform: | Size: 197632 | Author: xgh | Hits:

[VHDL-FPGA-Verilog] VCchuankou

Description: verilog ADPLL file with testbench
Platform: | Size: 206848 | Author: xgh | Hits:

[VHDL-FPGA-Verilog] a

Description: ADPLL of high level phase locked loop
Platform: | Size: 1471488 | Author: bc | Hits:

[Other] b

Description: A high-speed variable phase accumulator for an ADPLL architecture
Platform: | Size: 287744 | Author: bc | Hits:

[VHDL-FPGA-Verilog] ADPLL

Description: 全数字锁相环（adpll)的部分源程序代码，是其中最重要的部分。-All-digital phase-locked loop (adpll) part of the source code, is one of the most important part.
Platform: | Size: 2048 | Author: 林飞 | Hits:

[Other] adpll

Description: All digital phase locked loop based clock multiplier design. No off chip components
Platform: | Size: 187392 | Author: Abhishek | Hits:

[SCM] APL99

Description:  An All-Digital Phase-Locked Loop (ADPLL)-Based Clock Recovery
Platform: | Size: 394240 | Author: malijun | Hits:

[Software Engineering] 10.1.1.125.4046

Description: BUILDING AN RF SOURCE FOR LOW COST TESTERS USING AN ADPLL CONTROLLED BY TEXAS INSTRUMENTS DIGITAL SIGNAL
Platform: | Size: 88064 | Author: Kidane | Hits:

[Other] ADPLL

Description: 学习资料。一个关于信号处理软件ADPLL的使用说明，很有用。-Learning materials. A signal processing software ADPLL of the instructions, very useful.
Platform: | Size: 302080 | Author: fu | Hits:

[VHDL-FPGA-Verilog] a-adpll-based-on-fpga

Description: FPGA实现的VHDL语言的全数字锁相环-a adpll based on fpga
Platform: | Size: 4096 | Author: MIMI | Hits:

[File Format] ADPLL-patent

Description: 全数字锁相环的几个专利，全部为英文，很好的参考资料-DPLL patent
Platform: | Size: 411648 | Author: 程硕 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ADPLL

Description: verilog语言编写的fpga的全数字锁相环ADPLL程序-Verilog language FPGA all digital phase-locked loop ADPLL program
Platform: | Size: 270336 | Author: 伊尔 | Hits:

[ELanguage] ADPLL

Description: code for a counter which is used in the design of a Digital Phase Locked Loop.
Platform: | Size: 18432 | Author: Balakrishna C H | Hits:

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