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Description: 16位高速加法器,采用verilog语言编写,已经成功仿真,能够运行
Platform: |
Size: 2205 |
Author: modelsims |
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Description: 16位高速加法器,采用verilog语言编写,已经成功仿真,能够运行-16 high-speed adder using Verilog language has been successful simulation can be run
Platform: |
Size: 2048 |
Author: modelsims |
Hits: