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[Other resource] VHDL大作业－虞益挺036100486

Description: 全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
Platform: | Size: 88116 | Author: 熊辉波 | Hits:

[VHDL-FPGA-Verilog] VHDL大作业－虞益挺036100486

Description: 全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
Platform: | Size: 88064 | Author: 熊辉波 | Hits:

[VHDL-FPGA-Verilog] 100个vhdl设计例子

Description: 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233472 | Author: 杰轩 | Hits:

[SCM] VHDL范例

Description: 最高优先级编码器 8位相等比较器 三人表决器（三种不同的描述方式） 加法器描述 8位总线收发器：74245 （注2） 地址译码（for m68008） 多路选择器（使用select语句） LED七段译码 多路选择器（使用if－else语句） 双2－4译码器：74139 多路选择器（使用when－else语句） 二进制到BCD码转换 多路选择器 （使用case语句） 二进制到格雷码转换 双向总线（注2） 汉明纠错吗译码器 三态总线（注2） 汉明纠错吗编码器 解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilog] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45056 | Author: 蔡孟颖 | Hits:

[Documents] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Platform: | Size: 15360 | Author: 李成 | Hits:

[VHDL-FPGA-Verilog] vhdldesign

Description: 浮点加法器的VHDL算法设计 浮点加法器的VHDL算法设计-floating point adder VHDL algorithm design of the floating point adder VHDL Design Algorithm
Platform: | Size: 202752 | Author: yan | Hits:

[Other] jiafaqi

Description: 实现四位加法器的VHDL代码，里面含有全加器的代码-achieve four Adder VHDL code, which contains the full adder code
Platform: | Size: 1024 | Author: 丘志光 | Hits:

[Other] nbit_Adder

Description: VHDL——N位加法器设计-VHDL-- N-adder design RECOMMENDATIONS
Platform: | Size: 5120 | Author: 钱伟康 | Hits:

[ELanguage] ADDER8B

Description: 8位加法器VHDL 8位加法器VHDL-eight Adder VHDL e ight Adder VHDL eight Adder VHDL 8 Adder VHDL
Platform: | Size: 45056 | Author: | Hits:

[Documents] VHDL

Description: VHD设计实例8位加法器的设计分频电路数字秒表的设计-VHD Design 8 adder design of sub-frequency circuit design of digital stopwatch
Platform: | Size: 569344 | Author: yyy | Hits:

[VHDL-FPGA-Verilog] myproject

Description: 四位全加器，VHDL语言，max+plusII平台做的-Four full-adder, VHDL language, max+ PlusII platform to do
Platform: | Size: 56320 | Author: 邱飞 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 自编自写的ＶＨＤＬ代码，用于实现全加器功能，可能有误-, Directed and written in VHDL code, for the realization of full-adder function, may have mistaken
Platform: | Size: 4096 | Author: 金嘉 | Hits:

[VHDL-FPGA-Verilog] 5bit-adder-subtracter

Description: 5 bits 的加法器與減法器合併電路之原始程式製作 -5 bits of the adder circuit combined with the subtraction of the original browser program production
Platform: | Size: 53248 | Author: dajen | Hits:

[Other] adder

Description: 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
Platform: | Size: 38912 | Author: zhaozimou | Hits:

[VHDL-FPGA-Verilog] Half-Adder

Description: This is an example to implement an Half-adder for xilinx FPGA
Platform: | Size: 21504 | Author: DanCerv | Hits:

[VHDL-FPGA-Verilog] Half-Adder

Description: xilinx ISE平台提供1位半加法器，模块随模拟提供(Half- adder 1- bit design implemented in ISE XIlinx Design Suite. Module in VHDL language)
Platform: | Size: 21504 | Author: DanCerv | Hits:

[VHDL-FPGA-Verilog] kogge stone adder VHDL code

Description: Generic kogge-stone adder and testbench IN VHDL
Platform: | Size: 223603 | Author: spgp1306 | Hits:

[VHDL-FPGA-Verilog] SPANNING TREE ADDER 27-bit VHDL

Description: 27-bit spanning tree adder written in VHDL coding
Platform: | Size: 189982 | Author: spgp1306 | Hits:

[Other] Adder

Description: VHDL code for 4bit adder and full/half adders
Platform: | Size: 1334272 | Author: Tokyosn1 | Hits:
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