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[VHDL-FPGA-Verilog] adder4

Description: 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
Platform: | Size: 1024 | Author: olive | Hits:

[VHDL-FPGA-Verilog] cascaded_adder

Description: implementation of cascade adder with verilog plus testbench
Platform: | Size: 4096 | Author: shabnam | Hits:

[source in ebook] Chapter1-5

Description: 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 1580032 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[Other] adder_4

Description: 详细介绍了四位加法器的verilog代码，还包括详细的testbench代码。-Details of the four adder verilog code, also includes detailed testbench code.
Platform: | Size: 1024 | Author: kevin | Hits:

[Other] adder

Description: 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral description, ripple carry, the square root of the carry , with a simple testbench
Platform: | Size: 3072 | Author: D | Hits:

[VHDL-FPGA-Verilog] halfadder.v.tar

Description: Verilog Code for Half Adder Circuit with testbench code-Verilog Code for Half Adder Circuit with testbench code...
Platform: | Size: 1024 | Author: Dhaval | Hits:

[VHDL-FPGA-Verilog] fulladder.tar

Description: Verilog Code for Full Adder circuit with Testbench file-Verilog Code for Full Adder circuit with Testbench file...
Platform: | Size: 1024 | Author: Dhaval | Hits:

[VHDL-FPGA-Verilog] 64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc

Description: 64Bit Look Ahead Adder Verilog Code with Testbench
Platform: | Size: 2048 | Author: Anand | Hits:

[VHDL-FPGA-Verilog] ADDR

Description: 8位全加器，包括半加器verilog文件，全加器verilog文件，8位全加器verilog文件，和8位全加器测试testbench文件-8 full adder, including half adder, full adder Verilog file, Verilog file, 8 full adder Verilog files, and 8 full adder test testbench file
Platform: | Size: 141312 | Author: JJ | Hits:

[VHDL-FPGA-Verilog] CLA_20

Description: 用verilog语言编写的CLA_20文件。CLA_20是20位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 20 files. CLA 20 is 20 lookahead adder source code after the code verification function correctly, readers can write their own testbench code for verification.
Platform: | Size: 1024 | Author: huawei | Hits:

[VHDL-FPGA-Verilog] CLA_4

Description: 用verilog语言编写的CLA_4文件。CLA_4是4位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 4 files. CLA 4 is a four-ahead adder source code after the code verification function correctly, readers can write their own testbench code for verification.
Platform: | Size: 1024 | Author: huawei | Hits:

[VHDL-FPGA-Verilog] adder_carry_chain

Description: 使用verilog语言实现进位链加法器,quartus下编译，并使用modelsim进行了验证，内含carry_chain.v代码文件以及testbench文件-use verilog language,carry_chain adder
Platform: | Size: 3008512 | Author: maxiaobo | Hits:

[VHDL-FPGA-Verilog] 16Bit-Group-Ripple-Adder

Description: Verilog Testbench for 16Bit Group Ripple Adder
Platform: | Size: 29696 | Author: Raz | Hits:

[VHDL-FPGA-Verilog] float_adder

Description: 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
Platform: | Size: 82944 | Author: 聪明的Jerry | Hits:

[VHDL-FPGA-Verilog] verilog add4

Description: 分两部分，基于verilog的四位和八位加法器设计，用synopsys的VCS仿真工具进行功能仿真，掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.)
Platform: | Size: 512000 | Author: yzzls | Hits:

[VHDL-FPGA-Verilog] FP_adder

Description: 32 bit floating point adder with testbench
Platform: | Size: 11264 | Author: liki20 | Hits:

[VHDL-FPGA-Verilog] adder

Description: 实现了加法器功能，包含testbench(Implements the adder function)
Platform: | Size: 1024 | Author: 心向远方93 | Hits:

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