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[VHDL-FPGA-Verilog] 45561564

Description: 典型实例10.8 字符LCD接口的设计与实现 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects \ project folder inside 3. the distribution of the source file and pin in \ rtl folder inside 4. download files in \ download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.
Platform: | Size: 313344 | Author: 王磊 | Hits:

[Technology Management] c_xapp501

Description: 配置快速入门指南本应用指南讨论 Xilinx 的复杂可编程逻辑器件 (CPLD)、现场可编程门阵列 (FPGA) 和 PROM 系 列的配置与编程选项，并演示了各系列最常用的部分配置方法。-xilinx c_xapp501 spec
Platform: | Size: 549888 | Author: 小王王 | Hits:

[VHDL-FPGA-Verilog] XC4VLX60MB_Lab5_PROM_ISE91

Description: XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG s DOWNLOAD CABLE with the IMPACT software is continuously recordable BIT file to the FPGA, you can verify the results, such as Lab1 ~ Lab4 are conducted in this manner, the design. But in the end, if required to maintain the final version of the file, you need to first convert through BIT MCS file, then burn the file records to the PROM MCS inside, after the burn is complete, FPGA can set the M0, M1, M2 s pick Pin 000 (ie Mater Slave Mode), so off power after the next boot, FPGA from the PROM auto-complete Confogurtion, In order to keep this file can be permanent.-XCVLXMB the board Xilinx SRAM_BASED FPGA design is the main element Pieces, SRAM_BASED the FPGA, the design began to verify the results, may experience many changes, this time as long as the JTAG' s DOWNLOAD CABLE with the IMPACT software is continuously recordable BIT file to the FPGA, you can verify the results, such as Lab1 ~ Lab4 are conducted in this manner, the design. But in the end, if required to maintain the final version of the file, you need to first convert through BIT MCS file, then burn the file records to the PROM MCS inside, after the burn is complete, FPGA can set the M0, M1, M2' s pick Pin 000 (ie Mater Slave Mode), so off power after the next boot, FPGA from the PROM auto-complete Confogurtion , In order to keep this file can be permanent.
Platform: | Size: 794624 | Author: vkiy | Hits:

[VHDL-FPGA-Verilog] vga_pingpong

Description: 利用FPGA控制VGA输出在CRT显示器上实现乒乓球游戏，工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。在xilinx xc3s400调试通过-The FPGA to control the VGA output table tennis game on a CRT monitor, the project \ project file folder source files and pin assignment in \ rtl folder inside the folder download \ download file. Mcs, PROM mode downloaddownload the file, bit JTAG debug. Xilinx xc3s400 debugging through
Platform: | Size: 1021952 | Author: rooney | Hits:

[VHDL-FPGA-Verilog] Xilinx-Configuraon-Reference-

Description: 本应用笔记讨论的是Xilinx 的复杂可编程器件（CPLD）、现场可编程门阵列（FPGA）和PROM系列的配置和编程选项。它示意了每个系列的最常用的一些配置方法。-This application note of the discussion is the complex programmable device Xilinx (CPLD), field programmable gates array (FPGA) and PROM series of configuration and programming options. It found each series of some of the most common configuration method.
Platform: | Size: 353280 | Author: 崔健 | Hits:

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