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[VHDL-FPGA-Verilogshuzidianyabiao

Description: 系统基于EDA技术的智能数字电压表实现,以现场可编程门阵列(FPGA)为设计核心,集成于一片Xilinx公司的SpartanⅡE系列XC2S100E-6PQ208芯片上,在ISE环境下采用超高速硬件描述语言(VHDL)模块化编程,实现了电压的数据采集、转换、处理、显示等功能。本设计的特点在于能够测量的电压范围宽(0~50VDC),主要采用了分压原理,该系统具有集成度高、灵活性强、易于开发和维护等特点。-System based on EDA technology of intelligent digital voltmeter to achieve, to field programmable gate array (FPGA) for the design of the core, integrated in a Xilinx' s Spartan Ⅱ E Series XC2S100E-6PQ208 chip, in the ISE environment, use of ultra-high-speed hardware description language (VHDL ) modular programming, the voltage data acquisition, conversion, processing, display and other functions. The design features is the ability to measure the voltage range (0 ~ 50VDC), with a partial pressure of the main principles of the system with high integration, flexibility, ease of development and maintenance.
Platform: | Size: 15360 | Author: zhao | Hits:

[Windows DevelopPoint

Description: VHDL语言实现在16*16点阵显示模块上显示汉字。(EDA/SOPC开发平台)显示内容未输入,形式为16位字符串(0、1)显示0时对应点阵上的灯亮起,1的时候熄灭-VHDL language to display Chinese font on a 16 x 16 dot matrix display module. (EDA/SOPC development platform) , the form of a 16-bit string (0,1) “0”stand for light on,“1”stand for light off
Platform: | Size: 415744 | Author: 李冰恒 | Hits:

[VHDL-FPGA-Verilogfinaldesign_watch

Description: 基于VHDL的数字跑表源码,芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3,项目设计过程中,用EDA技术作开发手段,运用VHDL语言,实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for the development, the use of the VHDL language, from 0.01 seconds to 59 minutes 59 seconds 59 design.
Platform: | Size: 985088 | Author: huyanting | Hits:

[Software Engineeringdianzimimashuolunwen

Description: 为了使现在的电子密码锁更能智能化的管理,让人们更能方便的使用,让其具有更高的安全性和经济性,针对基于单片机的电子密码锁的不足之处,本文采用EDA技术,利用QuartusⅡ工作平台硬件描述语言,设计一种电子密码锁,并通过一片FPGA芯片实现。采用VHDL语言使用自顶向下的方法对系统进行了描述,并在FPGA芯片CycloneⅡ上实现。设计充分利用了FPGA的资源可编程特性,可高效率的对系统进行升级与改进。设计的密码锁可设置任意密码,比一般的四位密码锁具有更高的安全可靠性,因此,采用FPGA 开发的数字系统,不仅具有很高的工作可靠性,其升级与改进也极其方便,应用前景十分良好。-In order to make electronic locks now more intelligent management, so that people more convenient to use, let it have a higher level of security and economy, the inadequacy of microcontroller based electronic locks for, we use EDA technology by QuartusⅡ work platform hardware description language design an electronic lock, and through an FPGA chip. Methods of VHDL using a top-down system are described and implemented in the FPGA chip CycloneⅡ. Designed to take full advantage of the resources of FPGA programmable features, high efficiency of the system can be upgraded and improved. Design can set any password lock, password lock than the average of four has higher safety and reliability, therefore, the use of FPGA development of digital systems, not only has high reliability, it is also extremely easy to upgrade and improvement, prospects are very good.
Platform: | Size: 542720 | Author: 许家硕 | Hits:
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