Search - VHDL phase

[Other resource] VHDL范例

Description: 最高优先级编码器 8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句） LED七段译码多路选择器（使用if－else语句）双2－4译码器：74139 多路选择器（使用when－else语句）二进制到BCD码转换多路选择器（使用case语句）二进制到格雷码转换双向总线（注2）汉明纠错吗译码器三态总线（注2）汉明纠错吗编码器解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 42884 | Author: kerty | Hits:

[Other resource] VHDL-ysw

Description: 基于CPLD的棋类比赛计时时钟,第一个CNT60实现秒钟计时功能，第二个CNT60实现分钟的计时功能，CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能，当秒种计时模块计时到59时向分种计时模块进位，同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位，到1小时59分59秒时，全部清零。同时，开关K1可以在两小时内暂停秒钟计时模块，分钟计时模块和小时计时模块。各模块的VHDL语言描述如下：-CPLD-based time clock chess competitions, a CNT60 achieve seconds timing, CNT60 second minute of time to achieve functional, CTT3 completion of the two-hour time function. Module seconds into time - and-switch K1 phase minutes for a time module can be enabled When seconds time to time module to the 59 minute time rounding module, reset themselves. Similarly minute time module to the 59-hour time CTT3 module rounding to 1 hour 59 minutes 59 seconds, reset all. Meanwhile, switches K1 can be suspended within two hours time module seconds, minutes and hours of time metering module module. The module VHDL is described as follows :
Platform: | Size: 2716 | Author: 杨仕伟 | Hits:

[VHDL-FPGA-Verilog] 数字锁相环设计源程序

Description: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF
Platform: | Size: 120832 | Author: 杰轩 | Hits:

[SCM] VHDL范例

Description: 最高优先级编码器 8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句） LED七段译码多路选择器（使用if－else语句）双2－4译码器：74139 多路选择器（使用when－else语句）二进制到BCD码转换多路选择器（使用case语句）二进制到格雷码转换双向总线（注2）汉明纠错吗译码器三态总线（注2）汉明纠错吗编码器解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilog] FPGA_LMS

Description: VHDL写的LMS算法程序。利用本地正弦信号，根据LMS算法对输入信号进行跟踪。用以产生和输入信号同频同相的本地信号。-VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
Platform: | Size: 270336 | Author: 黄鹤 | Hits:

[VHDL-FPGA-Verilog] FIR31

Description: 设计一个线性相位FIR滤波器（31阶）输入8位，输出8位,H(n)={1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69,111,128,111,……2,1} H(n)具有对称性。输入信号范围 [±99，0，0，0， ±70，0，0，0， ±99，0，0，0， ±70，…]-Design a linear phase FIR filter (31 bands) 8 input, 8 output, H (n) = (1,2,0,-2,-2,1,6,6,-1,-13,-21,-11,22,69111128111, ... ... 2,1) H (n) has a symmetry. Input signal range [± 99,0,0,0, ± 70,0,0,0, ± 99,0,0,0, ± 70, ...]
Platform: | Size: 2641920 | Author: 陈金立 | Hits:

[VHDL-FPGA-Verilog] fifo_01

Description: 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[ELanguage] sub4

Description: 用VHDL语言编写的两个四位二进制数相减，其结果会出现进位-using VHDL prepared by the two four binary-phase reduction, and the results will be there to rounding
Platform: | Size: 32768 | Author: yanyuntao | Hits:

[Embeded-SCM Develop] VHDL_stepper-motor

Description: 用于CPLD的控制，VHDL编程，实现控制三相步进电机的正反转。-control for CPLD, VHDL programming, control of three-phase stepper motor rotating direction.
Platform: | Size: 281600 | Author: 胡迪 | Hits:

[Documents] changyongdevhdl

Description: 4位乘法器,4位除法器 8位数据锁存器,8位相等比较器,带同步复位的状态机,元件例化与层次设计,最高优先级编码器-four multipliers, dividers four eight data latches, and eight other phase comparators, synchronous reset with the state machine, the component level with the cases of design, the highest priority encoder
Platform: | Size: 11264 | Author: 刘思雄 | Hits:

[VHDL-FPGA-Verilog] magnitude

Description: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: | Size: 12288 | Author: 郝晋 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 数字式相位测量仪，基于FPGA的数字相位测量仪的制作-Digital phase-measuring instrument, based on the FPGA digital phase-measuring instrument production
Platform: | Size: 23552 | Author: 郑淑琴 | Hits:

[Software Engineering] phase

Description: 设计了一基于现场可编程门阵列（FPGA）的低频数字式相位测量仪。该测量仪包括数字式移相信号发生器和相位测量仪两部分，分别完成移相信号的发生及其频率、相位差的预置及数字显示、发生信号的移相以及移相后信号相位差和频率的测量与显示几个功能。其中数字式移相信号发生器可以产生预置频率的正弦信号，也可产生预置相位差的两路同频正弦信号，并能显示预置频率或相位差值；相位测量仪能测量移相信号的频率、相位差的测量和显示。两个部分均采用基于FPGA的数字技术实现，使得该系统具有抗干扰能力强, 可靠性好等优点。
Platform: | Size: 604160 | Author: 郑淑琴 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 基于EMP 7128的数字式相位测量仪相位测量仪-EMP 7128-based digital phase-measuring instrument measuring instrument phase
Platform: | Size: 9216 | Author: YAGIC | Hits:

[VHDL-FPGA-Verilog] DPLL(VHDL)

Description: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Platform: | Size: 13312 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 8位相等比较器含源代码，用VHDL语言编写，具体很高的实用性，供读者参考-8, phase comparator, such as with the source code, using VHDL language, the specific relevance of a high for the reader is referred to
Platform: | Size: 1024 | Author: lijinling | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: FIR滤波器的性能参数设计一个滤波器最基本的就是性能参数的,决定着滤波器的实际功能.比如阶数,截至频率。本文滤波器设计参数 ①输入,输出数据宽度10位 ②阶数为4阶的线性相位FIR滤波器， ③类型:带通 -FIR filter performance parameters The design of a filter is the most basic performance parameters, determines the actual filter function. For example, the order, as the frequency. In this paper, filter design parameters ① input and output data width of 10 ② order for the 4 order of the linear phase FIR filter, ③ Type: Band Pass
Platform: | Size: 3072 | Author: bobo | Hits:

[Windows Develop] Desktop

Description: DDS数字频率合成DDS由相位累加器、正弦查找表、D／A转换器和低通滤波器组成 -DDS DDS DDS from the phase accumulator, sine look-up tables, D/A converter and low-pass filter composed of
Platform: | Size: 1024 | Author: chenxiaofeng | Hits:

[VHDL-FPGA-Verilog] VHDL-dianti

Description: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。 ): 1统控制的电梯往返于1-9层楼。 2客要去的楼层数可手动输入并显示（设为A数）。 3梯运行的楼层数可自动显示（设为B数）。 4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升；当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降；当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门； 5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。注：此为word文档，但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER. ): An elevator control system and from 1-9 floors. 2, the number of passengers going to the floor can manually enter and display (Make A number). 3 ladder run automatically display the number of floors (Set B number). 4A> B, the system can output three-phase motor is transferred to the timing signal to lift up When A <B, the system can output three-phase motor to reverse the timing signal to the lift down When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door 5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch. Note: This is a word document, but inside the source code.
Platform: | Size: 34816 | Author: | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

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[Other resource] VHDL范例

[Other resource] VHDL-ysw

[VHDL-FPGA-Verilog] 数字锁相环设计源程序

[SCM] VHDL范例

[VHDL-FPGA-Verilog] FPGA_LMS

[VHDL-FPGA-Verilog] FIR31

[VHDL-FPGA-Verilog] fifo_01

[ELanguage] sub4

[Embeded-SCM Develop] VHDL_stepper-motor

[Documents] changyongdevhdl

[VHDL-FPGA-Verilog] magnitude

[VHDL-FPGA-Verilog] vhdl

[Software Engineering] phase

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] DPLL(VHDL)

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] vhdl

[Windows Develop] Desktop

[VHDL-FPGA-Verilog] VHDL-dianti

[VHDL-FPGA-Verilog] vhdl-ad9910

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