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[Other resource8051core_vhdl

Description: 8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.-8051 kernel (vhdl) This is version 1.1. Of the M C8051 IP core. FPGA operation. have the energy for the study.
Platform: | Size: 213197 | Author: efly | Hits:

[VHDL-FPGA-Verilog8051core_vhdl

Description: 8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.-8051 kernel (vhdl) This is version 1.1. Of the M C8051 IP core. FPGA operation. have the energy for the study.
Platform: | Size: 212992 | Author: efly | Hits:

[MiddleWareHDB3byVHDL

Description: 基于VHDL语言的HDB3码编译码器的设计 HDB3 码的全称是三阶高密度双极性码,它是数字基带传输中的一种重要码型,具有频谱中无直流分量、能量集中、提取位同步信息方便等优点。HDB3 码是在AMI码(极性交替转换码)的基础上发展起来的,解决了AMI码在连0码过多时同步提取困难的问题-Based on the VHDL language code HDB3 codecs design HDB3 code name is the third-order high-density bipolar code, it is the digital base-band transmission an important pattern, with no DC component spectrum, energy concentration, extraction bit synchronization information, such as the advantages of convenience. HDB3 code is in the AMI code (alternating polarity conversion code) developed on the basis of resolving the AMI code 0 yards too much even when difficult issues simultaneously extract
Platform: | Size: 257024 | Author: liangtao | Hits:

[Software Engineeringwirelesssensornetwork

Description: 研究在各种不同平台上对各种误差控制代码的性能分析和能量消费,并详细地对不同的限制误差控制代码用VHDL实现和仿真。-Research in a variety of different platforms on a variety of error control code, performance analysis and energy consumption, and to detail the different restrictions on the error control code and simulation using VHDL realize.
Platform: | Size: 521216 | Author: chenhang | Hits:

[Software EngineeringRobotic_Exploration_and_Landmark_Determination_us

Description: Sensing and planning are at the core of robot motion. Traditionally, mobile robots have been used for performing various tasks with a general-purpose processor on-board. This book grew out of our research enquiry into alternate architectures for sensor-based robot motion. It describes our research starting early 2002 with the objectives of obtaining a time, space and energy-efficient solution for processing sensor data for various robotic tasks. New algorithms and architectures have been developed for exploration and other aspects of robot motion. The research has also resulted in design and fabrication of an FPGA-based mobile robot equipped with ultrasonic sensors. Numerous experiments with the FPGA-based mobile robot have also been performed and they confirm the efficacy of the alternate architecture.
Platform: | Size: 1348608 | Author: moatasem momtaz | Hits:

[SCMyinpinfenxiyi

Description: 大学生电子竞赛论文报告-音频信号分析仪。主要利用频谱分析原理,频谱分析是把信号的能量用频率的函数显示出来-Undergraduate Electronic Thesis Competition Report- audio signal analyzer. The main principle of the use of spectrum analysis, spectrum analysis is used to signal the frequency of the energy function shown
Platform: | Size: 125952 | Author: song | Hits:

[VHDL-FPGA-VerilogEnergyEfficientVLSIArchitectureforLinearTurboEqua

Description: Energy efficient for turbo encoder decoder
Platform: | Size: 536576 | Author: suresh | Hits:

[VHDL-FPGA-VerilogIterativeDecodingofBinary

Description: In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder.
Platform: | Size: 1515520 | Author: suresh | Hits:

[VHDL-FPGA-VerilogMapAlgorithm

Description: However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination.
Platform: | Size: 1315840 | Author: suresh | Hits:

[VHDL-FPGA-VerilogVerilogLangRefManual

Description: Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.-Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.
Platform: | Size: 1283072 | Author: suresh | Hits:

[Program docwireless

Description: prohect energy efficient algorithm for wireless sensor network
Platform: | Size: 2314240 | Author: atul | Hits:

[VHDL-FPGA-VerilogADC_TLC549

Description: TLC549的VHDL驱动源码 已测试通过的TLC549的驱动源码 有转换使能和转换完毕标志-TLC549 the VHDL source code has been test driving the driving source through the TLC549 has converted to energy and the conversion complete flag
Platform: | Size: 1024 | Author: 123 | Hits:

[Software EngineeringGeneratingFPGA-AcceleratedDFTLibraries

Description: 关于DFT的文章,应用FPGA实现傅立叶变换。-Abstract—We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT). The partitioning strategy is a heuristic based on the DFT’s divide-and-conquer algorithmic structure and fine tuned by the feedback-driven exploration of candidate designs. We have integrated this approach in the Spiral linear-transform code-generation framework to support push-button automatic implementation. We present evaluations of hardware-software DFT implementations running on the embedded PowerPC processor and the reconfigurable fabric of the Xilinx Virtex-II Pro FPGA. In our experiments, the 1D and 2D DFT’s FPGA-accelerated libraries exhibit between 2 and 7.5 times higher performance (operations per second) and up to 2.5 times better energy efficiency (operations per Joule) than the software-only version.
Platform: | Size: 235520 | Author: 李然 | Hits:

[VHDL-FPGA-Verilogfive

Description: 并入串出寄存器完成双向含异步清0和同步时钟使能的4位加法器的VHDL描述,并对其进行波形仿真,确定结果正确。- Incorporated into the string to the register to complete the two-way with asynchronous clear and synchronous clock so that the VHDL description of the four adder energy and waveform simulation to determine the correct results.
Platform: | Size: 10240 | Author: qsp | Hits:

[VHDL-FPGA-Verilogsaomiao

Description: 基于vhdl语言的数码管动态扫描显示程序代码,同时加有数码管闪烁,超欠量程的led灯显示报警附加动能-Vhdl language-based digital control of dynamic scanning display program code, while adding a digital tube flashes, over and under range of led lights display alarm additional kinetic energy
Platform: | Size: 1024 | Author: 郭悦 | Hits:

[VHDL-FPGA-VerilogDAIMA-BLACK

Description: VHDL 语言的 能量感知的基础算法及sin 查表法 HEX,9-256-Energy VHDL language and perception on the basis of the algorithm sin lookup table HEX ,9-256
Platform: | Size: 2048 | Author: 涂欣 | Hits:

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