Search - VHDL bcd

[VHDL-FPGA-Verilog] anjian

Description: 按键输入模块（key）： --可编程延时发生器（数字同步机）的前端输入模块：0－9十个数字键按键输入模块原型 --前端模块：消抖 --对i0－i9十个输入端的两点要求： --（1）输入端要保证一段时间的稳定高电平 --（2）不能同时按下两个或多于两个的键 --后级模块：1、编码；2、可变模计数器 --编码模块：8线－4线（0－8 BCD码） --可变模计数器模块：以编码模块输出的32位BCD码为模值-button input module (key) :-- programmable delay generator (digital synchronous machine) the front-end input module : 0-2-9 10 numeric keys keys input module prototype-- front-end module : Consumers quiver-- the domain-Makes 10 input of the two requirements :-- (a) input to ensure a period of stability to I-- (2) can not be pressed together two or more two keys-- after class modules : one, coding; 2, variable Die counter-- Coding modules : 8-to-four (0-8 BCD)-- Variable Mode counter modules : coding module output to the 32 BCD value to Die
Platform: | Size: 2048 | Author: 汪汪 | Hits:

[SCM] VHDL范例

Description: 最高优先级编码器 8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句） LED七段译码多路选择器（使用if－else语句）双2－4译码器：74139 多路选择器（使用when－else语句）二进制到BCD码转换多路选择器（使用case语句）二进制到格雷码转换双向总线（注2）汉明纠错吗译码器三态总线（注2）汉明纠错吗编码器解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilog] count16

Description: count16.vhd 16位BCD计数器VHDL源程序-count16.vhd 16 BCD counter VHDL source
Platform: | Size: 1024 | Author: 杨奎元 | Hits:

[MPI] add_16_bcd

Description: 此程序采用VHDL语言，完成在16位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilog] add_32_bcd

Description: 此程序采用VHDL语言，完成在32位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[Other] bcd

Description: 实现bcd码与二进制码之间的相互转换功能，小于9时不变，高于九时加6功能-The realization of bcd code and binary code conversion function between, less than 9 am the same, higher than the 6 function plus 9:00
Platform: | Size: 7168 | Author: 汤仙君 | Hits:

[VHDL-FPGA-Verilog] LCDshow

Description: 基于VHDL的LCD显示程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the LCD display program, including complete source code, locking pin, as well as download files documents can be directly downloaded using
Platform: | Size: 19456 | Author: 陈泽涛 | Hits:

[Other] binarytobcd

Description: 实现二进制到BCD的转换,相关算法可参考相关文档资料-convert binary number to BCD
Platform: | Size: 3072 | Author: CoCo | Hits:

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[VHDL-FPGA-Verilog] anjian

[SCM] VHDL范例

[VHDL-FPGA-Verilog] count16

[MPI] add_16_bcd

[VHDL-FPGA-Verilog] add_32_bcd

[Other] bcd

[VHDL-FPGA-Verilog] LCDshow

[Other] binarytobcd

[SCM] binarytobcd_arithmetic

[VHDL-FPGA-Verilog] bin2bcd

[Windows Develop] bcd

[VHDL-FPGA-Verilog] MultBCD

[VHDL-FPGA-Verilog] bcd

[VHDL-FPGA-Verilog] BCD

[assembly language] binarytobcd

[VHDL-FPGA-Verilog] Seven-Segment-Decoder

[VHDL-FPGA-Verilog] xq_Test7

[VHDL-FPGA-Verilog] BCD

[VHDL-FPGA-Verilog] BCD

[VHDL-FPGA-Verilog] 2-Decimal-BCD-Decoder

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