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[Other] C2

Description: 功能更加完善的基于vhdl的数字时钟设计 有秒表，时钟，时期，闹钟的功能和整点报时，时间调整，日期调整，闹钟的设定 、、、、、、、 秒表有开始，暂停，清零等功能，且只有在暂停的情况下才能清零。-Function more complete VHDL-based design of the digital clock stopwatch, clock, time, alarm clock function and the whole point timekeeping, time adjustment, date, alarm clock settings ,,,,,,, stopwatch has started, pause, Clear and other functions, and only in the case of the suspension can be cleared.
Platform: | Size: 817152 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 基于VHDL环境下的秒表设计源代码 很好用的-Environment based on VHDL design source code stopwatch good use
Platform: | Size: 1024 | Author: Jim | Hits:

[Software Engineering] KESHE

Description: 基于FPGS的数字秒表设计文件 含有计时，停止，复位，清零功能-FPGS-based digital stopwatch design document contains a time, stop, reset, Clear Function
Platform: | Size: 295936 | Author: 豆豆 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
Platform: | Size: 44032 | Author: jyb | Hits:

[Embeded-SCM Develop] deCPLDVHDLshijong

Description: 基于CPLD的VHDL语言数字钟（含秒表）设计 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。 本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。 -CPLD based on the VHDL language digital clock (with stopwatch) design using a chip can be completed in addition to the clock source, buttons, speakers and display (LED) in addition to all functions of digital circuits. All digital logic functions are used in the CPLD device VHDL language. This design has a small and short design cycle (design process to achieve timing simulation), to facilitate debugging, fault rate is low and easy to modify the characteristics of the upgrade. The design uses a top-down, mixed input (input schematic- top-level file access and VHDL language input- the module program design) Design of digital clock, download and debug.
Platform: | Size: 95232 | Author: wuhuisong | Hits:

[VHDL-FPGA-Verilog] STOPWATCH

Description: 是基于FPGA/CPLD的跑表程序，可以存储记录多个运动员的跑步时间，是利用VHDL语言编写的，可以有助于学习EDA技术，可以参考学习，可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to the study, can help you complete VHDL language curriculum design.
Platform: | Size: 661504 | Author: 王亮 | Hits:

[OS program] b

Description: 基于VHDL的数字时钟设计与实现。。。。可以实现时钟，秒表-VHDL-based Design and Implementation of Digital clock. . . . Can achieve clock, stopwatch. .
Platform: | Size: 720896 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 基于fpga的vhdl语言，芯片是ep2c8系列，此代码实现的是秒表显示，毫秒到分的数码管显示，数码管是共阳的，分模块设计的，-The vhdl fpga-based language, the chip is ep2c8 series, this code is implemented stopwatch showed milliseconds to-point digital control, digital control is a total of Yang, the sub-module design,
Platform: | Size: 2525184 | Author: liyu | Hits:

[VHDL-FPGA-Verilog] 5

Description: 基于FPGA的数字秒表的VHDL设计,论文,有主要程序-FPGA-based VHDL design digital stopwatch, paper, a major program
Platform: | Size: 1024 | Author: 孤星寒 | Hits:

[VHDL-FPGA-Verilog] 3

Description: 】文章介绍了用于体育比赛的数字秒表的VHDL 设计, 并基于FPGA 在MAXPLUS2 软件下, 采用ALTRA 公司FLEX10K 系列的EPF10K10LC84- 4 芯片进行了计算机仿真-】 This article introduces digital stopwatch for sports competition in the VHDL design and FPGA-based software in MAXPLUS2, using ALTRA company FLEX10K series EPF10K10LC84-4 chip, the computer simulation
Platform: | Size: 50176 | Author: 孤星寒 | Hits:

[VHDL-FPGA-Verilog] digital-electronic-clock

Description: 基于VHDL的数字电子时钟的设计 实现计时，秒表，闹钟功能-VHDL-based design implementation digital electronic clock timer, stopwatch, alarm clock function
Platform: | Size: 216064 | Author: min | Hits:

[VHDL-FPGA-Verilog] A

Description: 基于CPLD的VHDL语言数字钟(含秒表)设计及程序 利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。-The VHDL language based on CPLD digital clock (including a stopwatch) design and program By using a chips in addition to clock source, buttons, the speaker and displays (digital tube) all the digital circuit function outside. All digital logic function in with VHDL language CPLD device realized. This design has small, the design cycle short (design process can be realized in the temporal simulation), convenient debug, low failure rate, modify upgrade easily etc. Characteristics.
Platform: | Size: 95232 | Author: ruohai | Hits:

[Other Embeded program] EDAmiaobiao

Description: 基于VHDL语言的EDA秒表作业设计，包括分频、秒表主体和数码管显示译码器，附有工程文件和管脚信息（EDA大作业西电02105143）-VHDL language based the EDA the stopwatch job design, including divide the stopwatch the main digital display decoder, with the project file and pin information (EDA Job Western Electric 02105143)
Platform: | Size: 433152 | Author: VanillaChow | Hits:

[VHDL-FPGA-Verilog] stopwatch-based-on-VHDL

Description: 基于VHDL的电子秒表的设计，使用VHDL语言描述一个秒表电路，利用QuantusII软件进行源程序设计，编译，仿真，最后形成下载文件下载至装有FPGA芯片的实验箱，进行硬件测试，要求实现秒表功能。-Design of electronic stopwatch based on VHDL
Platform: | Size: 1024 | Author: 煌釨 | Hits:

[SCM] secnew

Description: 基于FPGA的数字秒表设计。用VHDL语言设计数字秒表。-FPGA-based design of digital stopwatch. Design using VHDL digital stopwatch.
Platform: | Size: 385024 | Author: youjiaxin | Hits:

[VHDL-FPGA-Verilog] finaldesign_watch

Description: 基于VHDL的数字跑表源码，芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3，项目设计过程中，用EDA技术作开发手段，运用VHDL语言，实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for the development, the use of the VHDL language, from 0.01 seconds to 59 minutes 59 seconds 59 design.
Platform: | Size: 985088 | Author: huyanting | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: 基于CPLD的智能数字时钟VHDL设计，能实现时钟、秒表、闹钟、定时等功能-ntelligent digital clock CPLD VHDL-based design enables the clock, stopwatch, alarm clock, timer, and other functions
Platform: | Size: 411648 | Author: Steve | Hits:

[VHDL-FPGA-Verilog] MB

Description: 基于VHDL语言数字秒表设计,在FPGA实验平台下开发-Digital stopwatch design based on VHDL, FPGA experimental platform under development
Platform: | Size: 222208 | Author: 李耀 | Hits:

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