Location:
Search - VHDL IE
Search list
Description: 基于verilog HDL的自动售货机控制电路设计:
可以对5种不同种类的货物进行自动售货,价格分别为A=1.00,B=1.50,C=1.80,D=3.10,E=5.00 。售货机可以接受1元,5角,1角三种硬币(即有三种输入信号IY,IWJ,IYJ),并且在一个3位7段LED(二位代表元,一位代表角)显示以投入的总钱数，最大9.90元，如果大于该数值，新投入的硬币会退出,选择货物的输入信号Ia,Ib,Ic,Id,Ie和一个放弃信号In,输出指示信号为 Sa, Sb ,Sc ,Sd, Se 分别表示售出相应的货物,同时输出的信号yuan, jiao代表找零,相应每个脉冲代表找零相应的硬币，上述输入和输出信号均是一个固定宽度的脉冲信号。
Platform: |
Size: 1024 |
Author: chenyi |
Hits:
Description: UART(即Universal Asynchronous Receiver Transmitter 通用异步收发器)是广泛使用的串行数据传输协议。UART允许在串行链路上进行全双工的通信。-UART (ie Universal Asynchronous Receiver Transmitter Universal Asynchronous Receiver Transmitter) is a widely used serial data transfer protocol. UART allows for full-duplex serial link communications.
Platform: |
Size: 5120 |
Author: 陈 |
Hits:
Description: VHDL ieee标准 及 书籍-VHDL ieee standards and books
Platform: |
Size: 1520640 |
Author: haiwaw |
Hits:
Description: 实现代码，A、B为输入、Y为输出，它们为8位向量。OE为输出使能，低电平有效。IE为输入锁存时能，上升沿有效。Ci为进位输入，Co为进位输出。
S0、S1、S2为运算逻辑选择输入：
，用vhdl语言编写，基于数字电路。-Implementation code, A, B input, Y the output, they are 8-bit vector. OE to output enable, active low. IE when the input latch, rising edge and effective. Ci for the Carry input, Co to carry out. S0, S1, S2 for the arithmetic logic selection input: using vhdl language, based on digital circuits.
Platform: |
Size: 1024 |
Author: youruo |
Hits:
Description: 4位自动换挡数字频率计设计
1、 由一个4位十进制数码管（含小数点）显示结果；
2、 测量范围为1Hz~9999KHz；
3、 能自动根据7位十进制的结果，自动选择有效数据的高4位进行动态显示（即量程自动转换），小数点表示是千位，即KHz；
4、 为检测设计正确与否，应将时钟通过PLL和手控分频器产生宽范围的多个频率来测试自动换档频率计功能。
-4 automatic transmission design a digital frequency meter, by a 4 decimal digital tube (including the decimal point) shows the results 2, the measuring range 1Hz ~ 9999KHz 3, can automatically according to seven decimal results, automatically select valid data dynamic display of high 4 (ie, automatic range conversion), the decimal point that is 1000, which KHz 4, for the detection of design right or not, should be through the PLL and clock dividers generate wide range of manual multiple frequency Test automatic transmission frequency counter function.
Platform: |
Size: 354304 |
Author: 李伦特 |
Hits:
Description: 图象匹配中最常用的是基于面积的匹配，该匹配方法是把一幅图象中某一象点的灰度邻域作为模板，在另一幅图象中搜索具有相同(或相似)的灰度值分布的对应点的邻域，从而实现两幅图象的匹配〔2，。在搜索过程中，通常是以互相关函数作为两个搜索邻域间的相似性测度。
-this ie a program is in the inviroment.we can use it bring a lot of benefit to us.
Platform: |
Size: 848896 |
Author: sam |
Hits:
Description: VHDL编的按键去抖，可以实现对目前的显示取反，即1、0、1、0 变换。-VHDL code of the key to shaking, can negate the current display, ie 1,0,1,0 transformation.
Platform: |
Size: 228352 |
Author: lucy |
Hits:
Description: 使用vhdl语言设计的汽车尾灯控制电路。用六个发光二极管模拟6个汽车尾灯（汽车尾部左,右各3个），用两个开关作为转弯控制信号（一个开关控制右转弯，另一个开关控制左转弯）。当汽车往前行驶时（此时两个开关的都未接通），6个灯全灭。当汽车转弯时，若右转弯（即右转开关接通），右边3个尾灯从左至右顺序亮灭，左边3个灯全灭；若左转弯（即左转开关接通），左边3个尾灯从右至左顺序亮灭，右边3个灯全灭。当左、右两个开关同时接通时，6个尾灯同时明、暗闪烁。
-The taillights control circuit using VHDL language design. Analog 6 automobile taillights (left of the rear of the car, the right of each 3) with six light emitting diodes, as a turn with the two switches the control signal (a switching control right turn, and another switch controls the left turn). When Previous traveling of the vehicle (when the two switches at this time none of ON), six light Quanmie. When the car turns, if the right turn (right turn switch is turned on), the right three taillights from left-to-right order of light off the left three light Quanmie left turn (ie turn left switch is turned on), the left The right-to-left order of a taillight light off, the right of three lights all off. When the left and right two switches simultaneously, 6 taillights and dark flashing.
Platform: |
Size: 137216 |
Author: 陈小龙 |
Hits:
Description: Construct VHDL models for 74-139 dual 2-to-4-line decoders using three
description styles, i.e., behavioral, dataflow and structural descriptions. Synthesize
and simulate these models respectively in the environment of Xilinx ISE with the
ModelSim simulator integrated. When simulating these models, test vector(s) are
required to stimulate the units under test (UUT). Reasonable test vectors are designed
and created by your own as sources added to your VHDL project.-Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, ie, behavioral, dataflow and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector (s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.
Platform: |
Size: 310272 |
Author: 胡珩 |
Hits:
Description: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-The functionality of this module is to verify the implementation and PC, the basic functions of the serial communication. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepte
Platform: |
Size: 607232 |
Author: 饕餮小宇 |
Hits: