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Description: 输入时钟20M，波特率为9600，实现串口收发功能，通过修改内部分频系数可实现其它波特率的收发-Input clock 20M, the baud rate for 9600, Serial transceiver functions, by modifying the frequency of some other baud rate coefficient can realize the transceiver
Platform: |
Size: 7168 |
Author: 杨启勇 |
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Description: -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在
--PC机上安装一个串口调试工具来验证程序的功能。
-- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控
--制器，10个bit是1位起始位，8个数据位，1个结束
--位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实
--现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是
--9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间
--划分为8个时隙以使通信同步.
--程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome"
--字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制
--数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at
- PC machine on the installation of a serial debugging tools to verify the function of the procedure.
- Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control
- System, and 10 bit is a start bit, 8 data bits, 1 Ending
- Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real
- Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are
- 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time
- Is divided into eight time slots in order to enable synchronous communication.
- Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome"
- String (serial debug tools is set to accept by way of A
Platform: |
Size: 65536 |
Author: johnson |
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Description: fpga的串口读写程序，经硬件测试成功，波特率9600.可以改变分频值适应不同的时钟和波特率-fpga serial read and write procedures, by the hardware to test the success of 9600 baud rate. frequency value can be changed to adapt to a different clock and baud rate
Platform: |
Size: 384000 |
Author: cjy |
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Description: 最简单的UART发送程序，vhdl编写，系统时钟40M，波特率9600，外Load有效（一个高脉冲）即向PC发送一个字节0X-UART to send the simplest procedures, vhdl prepared, the system clock 40M, baud rate 9600, outside the Load effective (a high-pulse) to the PC sends a byte 0X55
Platform: |
Size: 451584 |
Author: wangxue |
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Description: 一个简单的uart 源码，接收一个字符并发回，通过测试，可以使用的，输入时钟12mhz,发送速率96-A simple uart source code, receiving a character and send back through the test, can be used, input clock 12mhz, sending rate 9600
Platform: |
Size: 379904 |
Author: wmd |
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Description: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-The functionality of this module is to verify the implementation and PC, the basic functions of the serial communication. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepte
Platform: |
Size: 607232 |
Author: 饕餮小宇 |
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