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[Com Port串口通讯VHDL源码

Description: 采用VHDL编写的串口通信。
Platform: | Size: 411533 | Author: yfy871216@sina.cn | Hits:

[Embeded-SCM Developkeyboard_apr9600

Description: 这是用PIC单片机控制键盘和APR9600芯片,实现语音功能的程序。可以录音,放音,录制一段或多段。附带APR9600的资料,可以修改程序,实现更多的功能-PIC keyboard and Voice chip, which features the voice procedures. Can recording, playback, recording or section of the. Fringe Voice of information, we can modify the program to achieve additional functionality
Platform: | Size: 694272 | Author: 陈燕 | Hits:

[VHDL-FPGA-Verilogyyin

Description: 这是一个语音程序,通过VHDL编译了.大家可以直接调用.其中还包括了键盘程序有需要可以下来-This a voice procedures, through a VHDL compiler. you can directly call. It also includes a keyboard procedures need to look at it down
Platform: | Size: 169984 | Author: 李飞 | Hits:

[VHDL-FPGA-Verilogpcm(8)

Description: 语音编码的VHDL源码,已经调试通过.压缩文件中包括调试过程代码.-speech coding VHDL source code, debugging has been adopted. Compressed files to include debugging code.
Platform: | Size: 79872 | Author: zhangruqi | Hits:

[SCMTaxi

Description: 接受里程传感器的脉冲输入(在本方案中使用PWM模拟替代传感器脉冲),并对脉冲进行计量,继而转换成里程; 􀂋 采用现行出租车计价系统的计算方法,对行驶里程进行计费; 􀂋 提供友好的用户界面,并具有语音提示功 能。 基于凌阳单片机!-Accept the mileage sensor pulse input (in this program using alternative sensors analog PWM pulse), and pulse measuring, and then converted into mileage
Platform: | Size: 560128 | Author: 冯旭升 | Hits:

[VHDL-FPGA-Verilogclock

Description: 数字钟的程序,功能说明如下所示: 1.完成秒/分/时的依次显示并正确计数; 2.秒/分/时各段个位满10正确进位,秒/分能做到满60向前进位; 3.定时闹钟:实现整点报时,通过语音设备来实现具体的报时; 4.时间设置,也就是手动调时功能:当认为时钟不准确时,可以分别对分/时钟进行调整 5.可以选择使用12进制计时或者24进制计时。 使用QuartusII6.0编译仿真通过,语言使用的是VHDL,可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[VHDL-FPGA-Verilog20

Description: FPGA语音通信平台设计实例哦-FPGA platform for voice communications design example Oh
Platform: | Size: 55296 | Author: 王洪亮 | Hits:

[VHDL-FPGA-Verilogyuyin

Description: 在FPGA上实现声卡接口,电子琴,滤波比较器,最终实现语音通信 -In the FPGA to achieve the sound card interface, flower, filter comparators, the eventual realization of voice communications
Platform: | Size: 55296 | Author: wangmixia | Hits:

[Speech/Voice recognition/combinerecognition

Description: 语音识别的源码可用于语音识别。。。。。语音识别 的源码可用于语音识别-Speech recognition source code can be used for speech recognition. . . . . Speech recognition source code can be used for speech recognition
Platform: | Size: 4096 | Author: xixi | Hits:

[Embeded-SCM DevelopAIC

Description: 使用FPGA/CPLD设置语音AD、DA转换芯片AIC23,FPGA/CPLD系统时钟为24.576MHz 1、AIC系统时钟为12.288MHz,SPI时钟为6.144MHz 2、AIC处于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、帧同步在96KHz-The use of FPGA/CPLD set voice AD, DA conversion chip AIC23, FPGA/CPLD system clock for the 24.576MHz 1, AIC system clock is 12.288MHz, SPI clock is 6.144MHz 2, AIC is in master mode 3, input bit length 16bit output bit length 16bit MSB first 4, frame synchronization at 96KHz
Platform: | Size: 2048 | Author: 张键 | Hits:

[assembly languagedianhuanyuanchengkongzhi

Description: 电话智能遥控器主要包括电话振铃检测电路,电话自动摘机和挂机电路,DTMF信号解码电路,语音提示急电路,音频放大电路,以及控制心脏CPU电路-Telephone remote control including smart phones ringing detection circuit, telephone and hang up automatically pick circuit, DTMF signal decoding circuit, urgent voice circuits, audio amplifier and the control of the heart CPU circuit
Platform: | Size: 7168 | Author: 卿卿 | Hits:

[Othertraficlightwhitsouth

Description: 这是一个带有语音功能的交通灯控制器,需要的朋友可以拿去-This is a voice-enabled with a traffic light controllers, the friends need to be taken to see
Platform: | Size: 504832 | Author: 陈彦 | Hits:

[Voice Compressyuyintongxin

Description: 基于CPLD的语音通信系统设计与实现毕业设计 原版包括程序源码,各部分仿真图,框图-CPLD-based voice communications system design and implementation of the design of the original graduate program, including source code, the part of simulation diagram, block diagram
Platform: | Size: 3988480 | Author: 李卫东 | Hits:

[Multimedia programADPCM_audio_codec

Description: ADPCM语音编解码电路设计及FPGA实现。利用FPGA进行ADPCM编码与解码。-ADPCM voice codec circuit design and FPGA realization. FPGA for use ADPCM encoding and decoding.
Platform: | Size: 125952 | Author: 水牛EDA | Hits:

[VHDL-FPGA-VerilogBIN_BCD

Description: 用硬件描述语音实现二进制数据转换成BCD数据-Using hardware description voice to achieve the binary data into BCD data
Platform: | Size: 620544 | Author: sleeeeeeep | Hits:

[VHDL-FPGA-Verilogdianyabiao

Description: 基于ISD4004的语音报值交直流电压表的设计:本文介绍了基于语音芯片ISD4004的语音报值交直流电压表的设计。电路由数据采集部分,A/D转换部分,键盘与显示部分,单片机控制部分,语音报值部分和扩展功能部分组成。电路使用了并行与串行总线相结合的方式,使设计与编程灵活简便。创意新颖有趣,富于人性化,避免了频繁观察仪器显示之苦,对减轻工程技术人员的工作量和提高工作效率现实意义。-ISD4004 voice-based value of AC and DC voltage at the design table: In this paper, based on the voice chip ISD4004 voice at the value of AC-DC voltage meter design. Part by the data acquisition circuit, A/D conversion of part of the keyboard and display, single-chip control of the reported value of part of speech and expand the functional parts. The use of a parallel circuit with a combination of serial bus, so as to enable convenient and flexible design and programming. Innovative ideas interesting and full of humanity, to avoid the frequent observation shows that the hardship of equipment, engineering and technical personnel to reduce workload and improve the efficiency of practical significance.
Platform: | Size: 475136 | Author: song | Hits:

[VHDL-FPGA-Veriloge2prwctrl

Description: EEPROM芯片读写控制器的VHDL语音程序设计-EEPROM chip to read and write controller VHDL Voice program design
Platform: | Size: 1024 | Author: lalo | Hits:

[Crack HackLogistichecat

Description: 将猫映射(cat map ) 与Logist ic 映射相结合, 构造了一种语音加密算法. 该算法首先将语音数据堆叠成二维, 然后利用二维猫映射将数据的位置置乱, 最后利用一维Logist ic 映射构造替换表, 对数据进行扩散.-The cat map (cat map) and Logist ic mapping the combination of a voice encryption algorithm is constructed. The algorithm first voice data stacked into two-dimensional, and then use two-dimensional cat map the location of the data scrambling and finally the use of one-dimensional Logist ic mapping structure to replace the table, the data spread.
Platform: | Size: 388096 | Author: 刘非 | Hits:

[Othereda

Description: eda实验时钟电路系统由秒时钟产生电路、走时电路模块、数字显示模块、校时模块、语音报时模块、工业控制模块-eda test clock circuit generated by the second clock circuit, the circuit blocks away, the digital display module, the campus module, voice timekeeping module, industrial control modules
Platform: | Size: 2639872 | Author: 樱花烬 | Hits:

[File Formatdaima

Description: 此程序可以对语音信号进行编码压缩等功能,并且可以预测编码-This program can be coded and compressed voice signal and other functions, and can be predictive coding
Platform: | Size: 2048 | Author: 王星龙 | Hits:
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