Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification. Platform: |
Size: 79872 |
Author:sundan |
Hits:
Description: 用verilog编写实现的以太网控制器（MAC）源码，解压后用ISE打开工程即可。-Prepared using verilog implementation Ethernet Controller (MAC) source code, open the project after decompression can be used ISE. Platform: |
Size: 142336 |
Author:陈阳 |
Hits:
Description: 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-========================
10GE MAC Core
========================
------------------------
1. Directory Structure
------------------------
The directory structure for this project is shown below.
.
|-- doc - Documentation files
|
|-- rtl
| |-- include - Verilog defines and utils
| `-- verilog - Verilog source files for xge_mac
|
|-- sim
| |-- systemc - SystemC simulation directory
| `-- verilog - Verilog simulation directory
|
`-- tbench
|-- systemc - SystemC test-bench source files
`-- verilog - Verilog test-bench source files
------------------------
2. Simulation
------------------------
There are two simulation environments that can be used to validate the code.
The verilog simulation is very basic and meant for those who want to look
at how the MAC operates without going through the effort of setting up SystemC.
The SystemC environment is more sophisticated and covers Platform: |
Size: 899072 |
Author:xuchao |
Hits:
Description: verilog描述的以太网MAC层源代码，功能正确，已经在FPGA开发板上测试！需要的赶紧下-verilog description of the Ethernet MAC layer source code, function correctly, has been tested in the FPGA development board! Need to hurry the next! ! ! Platform: |
Size: 56320 |
Author:WangYong |
Hits:
Description: Demux modules and test simulations with various combinations of input and output vectors.I am new to Verilog.I am learning it through a electronic system design course on my college.I am interested in downloading a single .zip file from this site,Verilog code for MAC data layer protocol.I hope you will consider my request. Platform: |
Size: 5120 |
Author:Igor |
Hits:
Description: 以太网MAC网卡的Verilog源代码，可以节省TCP/IP协议的设计开发时间。-Verilog source code for Ethernet MAC network card, you can save the TCP/IP protocol design and development time. Platform: |
Size: 125952 |
Author:lxk |
Hits:
Description: 非常详细的千兆以太网MAC verilog代码，可以供硬件设计时有关网络的开发参考-Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference Platform: |
Size: 704512 |
Author:瞿鑫 |
Hits:
Description: 10G高速以太网mac VERILOG源码
可仿真可实现-10G high speed Ethernet MAC verilog code
can be used for synthesis or inplementation Platform: |
Size: 789504 |
Author:王凯 |
Hits:
Description: MAC芯片LAN91C111驱动源码，quartus开发环境，Verilog HDL开发语言。自己编写调试通过。对FPGA控制MAC开发者非常有用。-MAC chip LAN91C111 driver source code, quartus development environment, Verilog HDL development language. Write debugging through their own. Very useful for FPGA control MAC developers. Platform: |
Size: 36864 |
Author:gsw |
Hits:
Description: this is a Verilog code for MAC Wrapper used in TCP IP suite that is used to extract MAC function TCP frame-this is a Verilog code for MAC Wrapper used in TCP IP suite that is used to extract MAC function TCP frame Platform: |
Size: 428032 |
Author:vinay |
Hits:
Search - VERILOG CODE FOR MAC