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[Other resource] Synopsys

Description: Synopsys 8051 IP core documentation.
Platform: | Size: 1177291 | Author: nevinfu | Hits:

[Books] Synopsys Timing Closure Flow

Description: Synopsys Timing Closure Flow
Platform: | Size: 38389 | Author: dacibao | Hits:

[VHDL-FPGA-Verilog] DW8051

Description: 大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51
Platform: | Size: 664576 | Author: 李无志 | Hits:

[VHDL-FPGA-Verilog] Synopsys

Description: Synopsys 8051 IP core documentation.
Platform: | Size: 1176576 | Author: | Hits:

[VHDL-FPGA-Verilog] PCI_144

Description: -- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144---- Synopsys VHDL Solution using Xilinx XC7000 Library
Platform: | Size: 3072 | Author: processor | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237

Description: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Platform: | Size: 207872 | Author: 上面的 | Hits:

[VHDL-FPGA-Verilog] Lab11

Description: 32bits FIFO with synchronizer. pass the synthesis using Synopsys tools-bits FIFO with synchronizer. Pass the sy nthesis using Synopsys tools
Platform: | Size: 60416 | Author: 王琪 | Hits:

[Other] Designing_with_Quartus

Description: 1)Learn more about the capabilities in Quartus: 2)Learn to use different design entry techniques 2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor, Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic -1) Learn more about the capabilities in Qua rtus : 2) Learn to use different design entry techniqu es 2) Design entry methods available within Qua rtus Text editor, Block diagram/schematic file editor, Quartus interface with design entry/synthesi s tools from Exemplar, Synopsys. Synplicity and Viewlogic
Platform: | Size: 2713600 | Author: Jawen | Hits:

[Other] VerilogandVHDL

Description: Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.-Verilog and VHDL state machine design, English pdf format State machine design techniques for Ve rilog and VHDL Abstract : Designing a synchronous finite state Another w ay of organizing a state machine (FSM) is a commo n task for a digital logic only one logic block as shown in engineer. This paper will discuss a var iety of issues regarding FSM design using Synop sys Design Compiler. Verilog and VHDL coding st yles will be 2.0 Basic HDL coding presented. Dif ferent methodologies will be compared using're al-world examples.
Platform: | Size: 113664 | Author: mingming | Hits:

[Books] synopsy_dc_ppt

Description: synopsys dc 中文ppt教材，比较详细! 可是SYnopsys公司培训的教材!难得的好东西!对学习Design compiler的人非常有帮助-synopsys dc Chinese ppt materials, more detail! But SYnopsys corporate training materials. rare good things! Design study of c ompiler are very helpful
Platform: | Size: 797696 | Author: 张华 | Hits:

[Other] sysdczw

Description: synopsys DC中文教程（ppt）-synopsys DC Chinese Tutorial (ppt)
Platform: | Size: 796672 | Author: | Hits:

[Other] VMMforSystemVerilog

Description: VMM for SystemVerilog中文版 Synopsys推崇SystemVerilog的设计和验证语言 这是一本很好的电子书-VMM for SystemVerilog Chinese version of Synopsys highly SystemVerilog design and verification language This is a very good e-book
Platform: | Size: 435200 | Author: stevephen | Hits:

[Software Engineering] DesignCompilerFAQ

Description: synopsys DC FRQ 最流行的综合工具
Platform: | Size: 21504 | Author: tian | Hits:

[Other] Quick_Start_nlint

Description: UNIX下的硬件代码检查工具的使用，step by step.Synopsys很好的工具文档。-Hardware under UNIX code inspection tools, step by step.Synopsys very good tool for documentation.
Platform: | Size: 1388544 | Author: 君懿 | Hits:

[Technology Management] RTL-Implementation-Guide

Description: 想做一个合格的ic工程师么？这个文档告诉你怎样写高质量的rtl代码。这是SYNOPSYS注册用户才可下载的文档-Want a qualified engineer ic it? This document tell you how to write high quality code rtl. This is the Synopsys registered users can download the document
Platform: | Size: 265216 | Author: scounix | Hits:

[Linux-Unix] cla_dc

Description: a demo script of "carry lookahead adder" for synopsys design compiler
Platform: | Size: 2048 | Author: heyong | Hits:

[VHDL-FPGA-Verilog] brentkung_adder

Description: Synopsys的DesignWare库中采用的brentkung高速加法器Verilog源代码生成,附相关文档-Synopsys
Platform: | Size: 522240 | Author: zx | Hits:

[ARM-PowerPC-ColdFire-MIPS] vmm-1.0.1.tar

Description: VMM 文档加源码, synopsys公司很好的验证资料-VMM Document Canadian source, synopsys good company to verify the information
Platform: | Size: 6774784 | Author: sun | Hits:

[Other] Synopsys_8051

Description: MCU_8051的Synopsys，到现在，我还没有用过-MCU_8051 of Synopsys, until now, I have not used
Platform: | Size: 1439744 | Author: 黄伟 | Hits:

[VHDL-FPGA-Verilog] DW8051

Description: Synopsys 公司的DW8051源代码，用verilog编写的，代码很完整，可以仿真，对采用8051核做嵌入式的人很有帮助-Synopsys company DW8051 source code, written with Verilog, the code is complete, can be simulated using 8051 nuclear helpful people who do Embedded
Platform: | Size: 68608 | Author: jy | Hits:
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