Location:
Search - STM-1 VERILOG
Search list
Description: 一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现
Platform: |
Size: 3112 |
Author: xl |
Hits:
Description: 一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming
Platform: |
Size: 3072 |
Author: fredyu |
Hits:
Description: 用verilog语言设计一个二进制序列检测电路， 当输入有连续“1011”出现时有输出为‘1’， 否则为‘0’.-Verilog language used to design a binary sequence detection circuit, a continuous input " 1011" appears when the output is ' 1 ' , otherwise ' 0' .
Platform: |
Size: 1024 |
Author: 农晓 |
Hits: