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[Software Engineeringsoc

Description: docupmen f\or soc design/
Platform: | Size: 74752 | Author: bavi | Hits:

[Software EngineeringHowtochoosesystemdesign

Description: 如何选择系统设计方案,这个问题是目前 SOC芯片设计的一个热点!-How to choose system design methodologies?it is the key issue in the SOC chip design domain currently!
Platform: | Size: 359424 | Author: 杨涛 | Hits:

[VHDL-FPGA-Verilogsc_examples.tar

Description: some examples of SystemC to begin SoC modeling -some examples of SystemC to begin SoC modeling
Platform: | Size: 1675264 | Author: mizmiz | Hits:

[Documentssoc

Description: 系统级芯片开发板介绍 及选型,一般都集成LINUX 或者wince 可以为用户省去很多 基础的代码移植工作,而且该开发板经过多种安全认证,应该是你开发面目的不二之选。-system on chip
Platform: | Size: 3950592 | Author: hongri119 | Hits:

[VHDL-FPGA-VerilogSystemC_for_SOC

Description: 为了辅助大家学习《SystemC片上系统设计》一书,方便大家阅读、理解、实践SystemC。大部分代码在Microsoft Visual Studio 6.0上编译通过,另有一些代码无法在个人电脑上使用,可以在工作站的Sun Solaris上编译通过。建议大家带着批评而不是崇拜的眼光来学习这些代码。 SystemC Core Language library 201是SystemC核心语言库,可以在个人电脑上运行。 SystemC MasterSlave Library201是SystemC核心Master/Slave库,可以在个人电脑上运行。 这两个库在运行前需要编译。-In order to assist them to learn " SystemC SoC design," a book so as to facilitate reading, understanding, practice SystemC. Most of the code in Microsoft Visual Studio 6.0 on the compile, while some code can not be used in personal computers, workstations, Sun Solaris can be compiled through. Suggest that you not worship with the eyes of critics to learn the code. SystemC Core Language library 201 is the SystemC core language library that can be run on personal computers. SystemC MasterSlave Library201 is the core SystemC Master/Slave Library, can be run on personal computers. The two libraries to compile before running.
Platform: | Size: 2450432 | Author: | Hits:

[Embeded-SCM Develop[R.Reis]Design_of_Systems_on_a_Chip_Design_and_Tes

Description: 比较经典的SOC设计与测试方法培训教材 第一篇: 概述 第二篇:系统规划 第三篇:测试流程 第四篇:ATPG 第五篇:时序逻辑ATPG和DFT 第六篇:可测试性 第七篇:BIST 第八篇:嵌入式core测试 第九篇:Memory 测试 -Starting with a basic overview of system-on-a-chip (SoC) including definitions of related terms, this text explains SoC design challenges, together with developments in SoC design and and test methodologies.
Platform: | Size: 2127872 | Author: 读卡 | Hits:

[AI-NN-PRSupportvectormachinebasedbatterymodelforelectricve

Description: The support vector machine (SVM) is a novel type of learning machine based on statistical learning theory that can map a nonlinear function successfully. As a battery is a nonlinear system, it is difficult to establish the relationship between the load voltage and the current under different temperatures and state of charge (SOC). The SVM is used to model the battery nonlinear dynamics in this paper. Tests are performed on an 80Ah Ni/MH battery pack with the Federal Urban Driving Schedule (FUDS) cycle to set up the SVM model. Compared with the Nernst and Shepherd combined model, the SVM model can simulate the battery dynamics better with small amounts of experimental data. The maximum relative error is 3.61 .
Platform: | Size: 179200 | Author: alice | Hits:

[Embeded-SCM Develop053747r00ZB_MWG-2005_09_12_Chipcon-SoC

Description: Chipcon公司推出的世界上第一个真正的系统级芯片(SoC)的ZigBeeTM-Chipcon Delivers on World’s First True System-on-Chip (SoC) ZigBeeTM Solution
Platform: | Size: 24576 | Author: gulijun | Hits:

[matlabBandpassSignalGen

Description: generation of wideband high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma–delta modulator chip. Via increasing the order of the one-bit bandpass sigma–delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma–delta modulator chip s production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.- generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma–delta modulator chip. Via increasing the order of the one-bit bandpass sigma–delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma–delta modulator chip s production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.
Platform: | Size: 5120 | Author: Nupur Naik | Hits:

[SCMGC01100111

Description: GC0111 是格科微电子(上海)有限公司2010 年最新研发的一款SOC 芯片, 将Sensor 和协处理器整合到了一颗芯片中,能实现的功能包括:支持EMI 接口 的sensor 预览/拍照/录像、SPI 接口的sensor 预览/拍照/录像、USB1.1 / USB2.0 full speed、 JPEG 压缩以及提供软T 卡、软Touch panel 的全套解决方案。GC0111 使得MTK 6223D/Infineon ULC3 等低端平台加一颗sensor 变成多媒体手机,降 低客户成本。 GC0110 是格科微电子(上海)有限公司最新推出的支持SPI 协议的CMOS 图像传感器芯片,采用GalaxyCore 最新的传感器工艺,并优化了电路结构,支 持JPEG 压缩,缩短拍照速度,提高用户体验,并支持录像功能。 -GC0111 is Geke Microelectronics (Shanghai) Co., Ltd. 2010, the latest development of a SOC chip Sensor and co-processor will be integrated into a single chip, to achieve the features include: support for EMI Interface The sensor Preview/photo/video, SPI interface sensor Preview/photo/video, USB1.1/USB2.0 full speed, JPEG compression and to provide soft-T card, soft Touch panel the full set of solutions. GC0111 Makes low-end platform MTK 6223D/Infineon ULC3 add a sensor into a multimedia mobile phone, drop Low customer cost. GC0110 is Geke Microelectronics (Shanghai) Co., Ltd. support the latest CMOS SPI protocol Image sensor chip, using the latest sensor technology GalaxyCore and optimize the circuit structure, support Support JPEG compression, reducing the speed camera to improve the user experience and supports video recording.
Platform: | Size: 2189312 | Author: PRAN | Hits:

[VHDL-FPGA-VerilogLEON3.Speed.SoC

Description: 基于LEON3处理器和Speed协处理器的复杂SoC设计实现-Speed based on LEON3 processor and the complexity of co-processor SoC design and implementation
Platform: | Size: 271360 | Author: 荣超群 | Hits:

[SCMSOC

Description: soc课件soc的发展趋势 soc 系统-courseware development trend of soc soc soc systems
Platform: | Size: 4302848 | Author: 尚国辉 | Hits:

[Windows MobileMobile-3D-Graphics-SoC

Description: Mobile 3D Graphics SoC
Platform: | Size: 5452800 | Author: eric | Hits:

[VHDL-FPGA-Verilogsoc-design

Description: 一本关于SOC的书,讲的很好,英文版的,如果对SOC感兴趣的网友,可以下载-A book about the SOC, speaking of the good, the English version, if users are interested in SOC, you can download to see
Platform: | Size: 2128896 | Author: clarkwang | Hits:

[Linux-UnixEncounte_-User_Guide

Description: SOC ENCOUNTER USER GUIDE 中文版-Soc encounter user guide(chinese edition), you can download it
Platform: | Size: 2929664 | Author: erin | Hits:

[SCM2

Description: The most important issues in SOC testing are controlling the whole process of SOC testing,Testing the UDL and interconnections,Testing cores with different functionalities coming from different vendors.
Platform: | Size: 11408384 | Author: sornasankar | Hits:

[Othermorgan.kaufmann.system-on-chip.test.architectures

Description: The SOC test problem is divided into 3 parts. 1)Core Wrapper Design 2)Test Access Mechanism design 3)Test scheduling
Platform: | Size: 9461760 | Author: sornasankar | Hits:

[ARM-PowerPC-ColdFire-MIPSSoC-verify-and-debug

Description: 摘要:介绍SoC(片上系统)软硬件协同验证中的软件仿真,给出验证uART(通用异步收发器)硬件接口的应用程序范例。利用GNU工具链开发SoC软硬件协同验证中的应用程序,并利用仿真器进行软件仿真,仿真结果正确。可以根据处理器的类型对GNU工具链进行配置,使开发流程适合所有GNu支持的处理器,方法具有一般性。根据开发者的具体需要,开发soc芯片的应用程序用于软硬件协同验证。-Abstract: SoC (system on chip) hardware and software co-verification of software simulation are given validation uART (Universal Asynchronous Receiver Transmitter) hardware interface, the application example. GNU tool chain developed by co-verification of SoC hardware and software applications, and use a software emulator simulation results are correct. According to the type of processor configuration on the GNU tool chain, the development process for all GNu supported processors, the method is general. According to the specific needs of developers, the development of applications for soc-chip hardware and software co-verification.
Platform: | Size: 336896 | Author: 李立 | Hits:

[matlabEVS-23_PHEV-all-electric-range-and-sensitivity-of

Description: PHEV ‘All electric range’ and fuel economy in charge sustaining mode for low SOC operation of the JCS VL41M Li-ion battery using Battery HIL
Platform: | Size: 278528 | Author: Sergii | Hits:

[Software EngineeringSOC.Verfication.Methodology

Description: SOC设计验证书籍,有关于芯片设计中的测试部分的研究-SOC design verification of books, the chip design on the part of the test
Platform: | Size: 3503104 | Author: 苏蔚 | Hits:
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