Search - RAM vh

[Other resource] RAM_VHDL_34

Description: RAM之VHDL描述 RAM之VHDL描述-RAM's VHDL description RAM's VHDL description RAM's VH DL described in VHDL's RAM
Platform: | Size: 5418 | Author: Nicholas | Hits:

[VHDL-FPGA-Verilog] RAM_VHDL_34

Description: RAM之VHDL描述 RAM之VHDL描述-RAM's VHDL description RAM's VHDL description RAM's VH DL described in VHDL's RAM
Platform: | Size: 5120 | Author: | Hits:

[VHDL-FPGA-Verilog] all_ram_20081116.tar

Description: vhdl cod for ram.For sp3e
Platform: | Size: 1126400 | Author: Fl0rin | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] ram

Description: ram的vhdl源代码在colloy实现-ram in the vhdl source code to achieve colloy
Platform: | Size: 1920000 | Author: mamou | Hits:

[VHDL-FPGA-Verilog] URISC

Description: 一个完整的带I/O和RAM，ROM的URISC,可以完成A+B/2的运算。实际上，通过对ROM的手工编程，可以实现8为数据的加减乘除，已经更加复杂的运算。-An ultimate URISC With I/Os, a RAM, a ROM,which can complete A+ B/2 calculations. In fact, through the ROM of the manual programming, it can do more calculations,such as A+B,A-B,A*B,A/B,and so on.
Platform: | Size: 5120 | Author: 王斌 | Hits:

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