Search - QUARTUS VHDL

[VHDL-FPGA-Verilog] 100个vhdl设计例子

Description: 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233472 | Author: 杰轩 | Hits:

[VHDL-FPGA-Verilog] LCD显示实验

Description: ALTERA NIOS处理器，用VHDL在QUARTUS下编写，用NIOS SHELL调试通过，实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
Platform: | Size: 35840 | Author: xf | Hits:

[VHDL-FPGA-Verilog] SPI接口音频Codec实验

Description: ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Platform: | Size: 34816 | Author: xf | Hits:

[Embeded-SCM Develop] memoire_alphabet

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
Platform: | Size: 1024 | Author: 秦拣俭 | Hits:

[VHDL-FPGA-Verilog] fifo数据缓冲器的vhdl源程序

Description: 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8* 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Platform: | Size: 1024 | Author: 夏社 | Hits:

[VHDL-FPGA-Verilog] quartus II中文用户教程(英文版的完全翻译）

Description: quartus II中文用户教程(英文版的完全翻译）,和一切爱好可编程器件的同仁共勉之-Quartus II Chinese user guide (English version of the full translation) love and all programmable devices colleagues share Zhi
Platform: | Size: 844800 | Author: 田晶昌 | Hits:

[VHDL-FPGA-Verilog] VHDL-Clock

Description: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Platform: | Size: 4096 | Author: 单单 | Hits:

[Software Engineering] verilog50%

Description: 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the simulation results. Design used EPM7064AETC44-7 CPLD. In QUARTUS II 4.2 software platform.
Platform: | Size: 187392 | Author: li | Hits:

[VHDL-FPGA-Verilog] VHDL-six

Description: 用VHDL语言实现六分频，并且已经通过编译和仿真。由此可举一反三，实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
Platform: | Size: 25600 | Author: philohb | Hits:

[Crack Hack] 3des-VHDL

Description: 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus
Platform: | Size: 95232 | Author: xin | Hits:

[VHDL-FPGA-Verilog] Quartus_vhdl

Description: 用QUARTUS编译通过的等精度频率计，我错误，但有几个警告（不影响设计）。我的毕业设计啊！！！ -QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
Platform: | Size: 44032 | Author: 刘刚 | Hits:

[VHDL-FPGA-Verilog] qqq

Description: 数字滤波器的vhdl源代码.在quartus上运行过,里面还有matlab的仿真文件.-Digital filter of the VHDL source code. In Quartus run-off, along with the simulation matlab file.
Platform: | Size: 26624 | Author: 萧勇 | Hits:

[VHDL-FPGA-Verilog] vhdl_crc

Description: 在quartus中用VHDL语言开发的crc校验-Quartus VHDL language used in the development of CRC Checksum
Platform: | Size: 163840 | Author: 夏杰 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: VHDL教程 ppt版绪论第一章 VHDL基本结构第二章 VHDL语言元素第三章 VHDL的描述风格第四章 VHDL的主要描述语句第五章组合逻辑电路设计第六章时序逻辑电路设计-Ppt version of VHDL Tutorial VHDL Introduction Chapter I Chapter II the basic structure of VHDL language element of VHDL in Chapter III Chapter IV describes the style of the main description language VHDL Chapter V combinational logic circuit design of Chapter VI of sequential logic circuit design
Platform: | Size: 1081344 | Author: 陈松 | Hits:

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[VHDL-FPGA-Verilog] 100个vhdl设计例子

[VHDL-FPGA-Verilog] LCD显示实验

[VHDL-FPGA-Verilog] SPI接口音频Codec实验

[Embeded-SCM Develop] memoire_alphabet

[VHDL-FPGA-Verilog] fifo数据缓冲器的vhdl源程序

[VHDL-FPGA-Verilog] quartus II中文用户教程(英文版的完全翻译）

[VHDL-FPGA-Verilog] VHDL-Clock

[Software Engineering] verilog50%

[VHDL-FPGA-Verilog] VHDL-six

[Crack Hack] 3des-VHDL

[VHDL-FPGA-Verilog] Quartus_vhdl

[VHDL-FPGA-Verilog] qqq

[VHDL-FPGA-Verilog] vhdl_crc

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] complete_projects

[VHDL-FPGA-Verilog] 100vhdl

[VHDL-FPGA-Verilog] lunwen

[VHDL-FPGA-Verilog] sinwave

[VHDL-FPGA-Verilog] vhdl-MIPS

[VHDL-FPGA-Verilog] vhdl

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