Search - Pulse-width modulation verilog

[VHDL-FPGA-Verilog] PWM

Description: 脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench-Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench
Platform: | Size: 348160 | Author: horse | Hits:

[VHDL-FPGA-Verilog] FPGAdezizhixingSPWMboChengXu

Description: 基于FPGA的自治型SPWM波形发生器的设计！正弦脉宽调制（SPWM）技术在以电压源逆变电路为核心的电力电子装置中有着广泛的应用，如何产生SPWM脉冲序列及其实现手段是PWM技术的关键。大家共同探讨哈！-FPGA based SPWM autonomy-based waveform generator design! Sinusoidal pulse width modulation (SPWM) technology in the voltage source inverter circuit as the core of the power electronic devices have a wide range of applications, how to generate SPWM pulse sequence and its implementation means PWM technology is the key. Kazakhstan investigate everyone!
Platform: | Size: 4096 | Author: 小喻 | Hits:

[VHDL-FPGA-Verilog] Verilog_example_of_pulse_width_modulation

Description: 学习verilog的一些资料。是脉宽调制控制的题目，以及源码和仿真文件。感觉代码风格还不错，可以学习一下。-Verilog study some of the information. Pulse width modulation control are the subject, as well as the source code and simulation files. Feel good style of code, you can study about.
Platform: | Size: 6305792 | Author: nothing | Hits:

[VHDL-FPGA-Verilog] Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex

Description: 来自于ALTERA官方网站。本文档详细介绍怎样利用MAX® II CPLD 来实现脉冲宽度调制(PWM)。本设计还利用了MAX II CPLD 的内部用户闪存振荡器，不需要采用专门的外部时钟。附有verilog源程序。-From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design also uses the MAX II CPLD' s internal oscillator user flash memory, without using a special external clock. With verilog source.
Platform: | Size: 291840 | Author: 无小品 | Hits:

[VHDL-FPGA-Verilog] pwm_task_logic

Description: 脉冲宽度调节（pwm）的verilog源码-Pulse width modulation (pwm) the verilog source
Platform: | Size: 1024 | Author: 李桃中 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 通过设置时钟实现脉冲宽度调制的verilog代码及测试(By setting the clock to achieve pulse width modulation of the Verilog code and test)
Platform: | Size: 155648 | Author: 老虎szjwl | Hits:

[Windows Develop] PWM

Description: 用Verilog实现的脉冲宽度调制程序，在quartus平台上测试成功。(Using Verilog implementation of pulse width modulation, in quartus platform test successfully.)
Platform: | Size: 151552 | Author: 莫五张 | Hits:

[VHDL-FPGA-Verilog] PWN

Description: Pulse Width modulation using Verilog HDL
Platform: | Size: 6144 | Author: liki20 | Hits:

[Other] SPWM

Description: 利用verilog语言实现正弦脉宽调制，经过调试可行(Using Verilog language to realize sinusoidal pulse width modulation)
Platform: | Size: 1024 | Author: 落魄小书童 | Hits:

[VHDL-FPGA-Verilog] DPWM

Description: 用Verilog实现数字脉宽调制模块，主要模块有锁相环、计数器、多路选择器(The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer)
Platform: | Size: 500736 | Author: lw1997 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] PWM

[VHDL-FPGA-Verilog] FPGAdezizhixingSPWMboChengXu

[VHDL-FPGA-Verilog] Verilog_example_of_pulse_width_modulation

[VHDL-FPGA-Verilog] Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex

[VHDL-FPGA-Verilog] pwm_task_logic

[VHDL-FPGA-Verilog] PWM

[Windows Develop] PWM

[VHDL-FPGA-Verilog] PWN

[Other] SPWM

[VHDL-FPGA-Verilog] DPWM

CodeBus www.codebus.net