Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - Nios II 7.2

Search list

[VHDL-FPGA-Verilog] is61lv25616_sram

Description:
Platform: | Size: 11264 | Author: 刘音 | Hits:

[Books] AnExperimentOfDE2_70

Description: 本文介绍的是一个具体的例子，给出了借助QUARTUS II 7.2和Nios II 7.2 IDE实现跑马灯实验的整个流程。-This article describes a specific example given by QUARTUS II 7.2 and Nios II 7.2 IDE Marquee experimental realization of the entire process.
Platform: | Size: 1060864 | Author: Wuxinmin | Hits:

[Other] software_72nios

Description: 这是Nios II 7.2 IDE中的工程模板，在8.0中有些没有，在此列出来，希望方便大家-This is the Nios II 7.2 IDE projects template, in 8.0, some not, in this list, I hope to facilitate
Platform: | Size: 208896 | Author: 云帆 | Hits:

[Technology Management] NIOS

Description: NIOS II中用到的C_C++函数的翻译-NIOS II used C_C++ function of the translation
Platform: | Size: 24576 | Author: 毛文娟 | Hits:

[Other] nios

Description: SOPC嵌入式开发软核NIOS ii 操作教程-SOPC embedded development soft core NIOS ii Operation Tutorial
Platform: | Size: 2936832 | Author: 李波 | Hits:

[VHDL-FPGA-Verilog] sopcIIC

Description: 该例子是基于sopc的IIC总线设计完整设计，分为硬件和软件部分，软件部分是用c语言编写的。该项目是个以完成的项目，据有较高的参考和经济价值。该例子是原来做过的项目。 整个项目是在Quartus II 7.0和nios IDE环境下开发。-This example is based on the IIC bus design sopc complete design, divided into hardware and software, the software part is written in c language. The project is to complete the project, according to the reference and a higher economic value. The example is a project originally done. The whole project is in the Quartus II 7.0 and the nios IDE development environment.
Platform: | Size: 13532160 | Author: bobo | Hits:

[VHDL-FPGA-Verilog] seg_7

Description: Altera DE系列开发板都可以参考的基于Nios ii 的数码管控制显示0-f程序-display 0-f with 7-segment display on Altera DE series board.
Platform: | Size: 122880 | Author: thomas yang | Hits:

[Software Engineering] DE2_NET

Description: DE2开发板例程源码，FPGA:EP2C35F256C6，代码基于quartus II 9.0以上的版本（随板光盘的为7.2的版本，在9.0以上的版本上编译通不过会报错）。该代码主要功能为FPGA对以太网通信，与PC机通信-In this demonstration, we will show how to send and receive Ethernet packets using the Fast Ethernet controller on DE2 board. We use the Nios II processor to send and receive Ethernet packets using the DM9000A Ethernet PHY/MAC Controller.
Platform: | Size: 1950720 | Author: chenxin | Hits:

[VHDL-FPGA-Verilog] DE2_NIOS_HOST_MOUSE_VGA

Description: 本代码为DE2开发板例程源码（EP2C35F672C6），项目基于quartus II 9.0（随板光盘为7.2版本以下，在9.0版以上编译会报错）。本项目实现一个USB画笔功能，通过FPGA控制USB口，USB口接上鼠标，通过XGA口外界显示设备，实现显示设备对鼠标移动轨迹的显示。-In this demonstration, we implement a Paintbrush application by using a USB mouse as the input device.This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector. We also implemented a video frame buffer with a VGA controller to perform the real-time image storage and display.
Platform: | Size: 2547712 | Author: chenxin | Hits:

[VHDL-FPGA-Verilog] DE2_SD_Card_Audio(quartus-9.0)

Description: 本代码为Altera DE2开发板例程源码（EP2C35F672C6)，quartus II 9.0以上版本均可编译（随板光盘为quartus II 7.2版在9.0以上版本上编译会报错）。本工程实现SD的音频播放器，即通过FPGA控制SD卡，读取SD的音频文件，通过WM8731进行播放。-In this demonstration we show how to implement an SD Card Music Player on the DE2 board, in which the music files are stored in an SD card and the board can play the music files via its CD-quality audio DAC circuits. We use the Nios II processor to read the music data stored in the SD Card and use the Wolfson WM8731 audio CODEC to play the music.
Platform: | Size: 10078208 | Author: chenxin | Hits:

CodeBus www.codebus.net