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[Other resource] Debussy

Description: Debussy是NOVAS Software, Inc(思源科技)發展的HDL Debug & Analysis tool，這套軟體主要不是用來跑模擬或看波形，它最強大的功能是：能夠在HDL source code、schematic diagram、waveform、state bubble diagram之間，即時做trace，協助工程師debug。 可能您會覺的：只要有simulator如ModelSim就可以做debug了，我何必再學這套軟體呢? 其實Debussy v5.0以後的新版本，還提供了nLint -- check coding style & synthesizable，這蠻有用的，可以協助工程師了解如何寫好coding style，並養成習慣。 下圖所示為整個Debussy的原理架構，可歸納幾個結論： -Debussy is NOVAS Software, Inc. (source technology) development of the HDL Debug
Platform: | Size: 57293 | Author: frankyq | Hits:

[Other resource] ModelSim6c_SE_Cracker

Description: crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL / Verilog simulator for CAD F PGA, board and IC design.
Platform: | Size: 292684 | Author: 陈亨利 | Hits:

[Other resource] Vhdl_Simulation_With_Modelsim

Description: Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
Platform: | Size: 52082 | Author: zhangyg | Hits:

[Other resource] ModelSim_Tutorial_V5.4

Description: 这是关于如何使用Mentor社的ModelSim软件的说明书。ModelSim是HDL simulator中最常用的一个。
Platform: | Size: 704733 | Author: 许京哲 | Hits:

[VHDL-FPGA-Verilog] ModelSim6c_SE_Cracker

Description: crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL/Verilog simulator for CAD F PGA, board and IC design.
Platform: | Size: 292864 | Author: 陈亨利 | Hits:

[VHDL-FPGA-Verilog] ModelSim_Tutorial_V5.4

Description: 这是关于如何使用Mentor社的ModelSim软件的说明书。ModelSim是HDL simulator中最常用的一个。-This is the agency on how to use Mentor
Platform: | Size: 704512 | Author: 许京哲 | Hits:

[VHDL-FPGA-Verilog] ADC_INTERFACE

Description: it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.
Platform: | Size: 6144 | Author: yasir ateeq | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
Platform: | Size: 31744 | Author: yasir ateeq | Hits:

[Other] dcfifo_sim_modelsim_ae_gui

Description: dcfifo verilog source code and modelsim simulator.
Platform: | Size: 19456 | Author: zhangbin | Hits:

[VHDL-FPGA-Verilog] quartus-and-modelsim-for-OFDM

Description: 关于quartus与modelsim 仿真-about quartus and modelsim simulator
Platform: | Size: 1553408 | Author: donglijun | Hits:

[VHDL-FPGA-Verilog] modelsim_guide_cn

Description: 使用ModelSim进行设计仿真ModelSim为HDL仿真工具，我们可以利用该软件来实现对所设计的VHDL或Verilog程序进行仿真，支持IEEE常见的各种硬件描述语言标准。可以进行两种语言的混合仿真，但推荐大家只对一种语言仿真。ModelSim常见的版本分为ModelSim XE和ModelSim SE两种，ModelSim版本更新很快-Design simulation using ModelSim HDL simulator ModelSim is, we can use the software to achieve the program designed to simulate VHDL or Verilog, to support a variety of common IEEE standard hardware description language. Mixture of two languages ​ ​ can be simulated, but recommend only one language simulation. Common version of ModelSim and ModelSim SE ModelSim XE is divided into two types, ModelSim version update soon
Platform: | Size: 342016 | Author: 谢明 | Hits:

[VHDL-FPGA-Verilog] vcs-fang-zheng-2

Description: VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式 使用的步骤和modelsim类似,都要先做编译,在调用仿真.-VCS-verilog compiled simulator is synopsys company' s products. The simulation very fast, and supports multiple call mode use similar steps and modelsim, we must do first compiled, the call simulation.
Platform: | Size: 179200 | Author: liyucai | Hits:

[VHDL-FPGA-Verilog] Modelsim-functional-simulation

Description: 介绍了Model Technology 公司的Modelsim XE II v5.6e的主要结构、属性设置、Modelsim XE II v5.6e与ISE5.2的软件接口，测试激励文件的建立以及Modelsim仿真分析方法。Altera公司QuartusII3.0仿真器(Simulator) 的主要结构、属性设置以及仿真分析方法。 -Introduced the Model Technology Modelsim XE II v5.6e company' s main structure, property, Modelsim XE II v5.6e and ISE5.2 software interface, build and test stimuli file Modelsim simulation analysis. Altera Corporation QuartusII3.0 Simulator (Simulator) the main structure, properties, settings, and simulation analysis.
Platform: | Size: 749568 | Author: zfj | Hits:

[VHDL-FPGA-Verilog] AssignmentP3

Description: Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, i.e., behavioral, dataflow and structural descriptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx ISE and ModelSim simulator. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.
Platform: | Size: 141312 | Author: 魏攸 | Hits:

[Software Engineering] ModelSim

Description: Modelsim仿真软件最基本的教程，如何新建工程，如何进行最简单仿真-this is a basic tutorial for Modelsim simulator
Platform: | Size: 708608 | Author: sunliuxun | Hits:

[Software Engineering] Assignment-3

Description: Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, i.e., behavioral, dataflow and structural descriptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx ISE and ModelSim simulator. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.-Assignment 3
Platform: | Size: 33792 | Author: 董振兴 | Hits:

[VHDL-FPGA-Verilog] assigment3

Description: Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, i.e., behavioral, dataflow and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.-Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, ie, behavioral, dataflow and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector (s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.
Platform: | Size: 310272 | Author: 胡珩 | Hits:

[Other] yimaqi_beh

Description: 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description types, i.e., behavioral, dataflow and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.
Platform: | Size: 1024 | Author: maria | Hits:

[VHDL-FPGA-Verilog] triangular_vhd

Description: This the triangular wave generation vhdl code to check the wave form in modelsim simulator-This is the triangular wave generation vhdl code to check the wave form in modelsim simulator
Platform: | Size: 1024 | Author: GOPALAKRISHNAN E | Hits:

[VHDL-FPGA-Verilog] modelsim se 10.1a crack

Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation software, offers a friendly simulation environment and is the industry's only single-core simulator supporting VHDL and Verilog mixed simulations. It uses direct optimization of the compiler technology, Tcl / Tk technology, and a single kernel simulation technology, compile and emulate fast, compiled code has nothing to do with the platform, easy to protect IP core, personalized graphical interface and user interface to speed up the user to debug wrong Provide a powerful means of choice for FPGA / ASIC design simulation software.)
Platform: | Size: 523264 | Author: 冰激凌很牛 | Hits:
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