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[Other resource] 除法器

Description: 通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。 设计平台：MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Description Language (VHDL) Description division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report
Platform: | Size: 50091 | Author: johnmad | Hits:

[Other resource] 译码器

Description: 通过对用硬件描述语言VHDL表示的某个专用部件（如中断控制器、差错控制码编码/译码器，此为译码器）的代码分析，构建它的逻辑结构，加深对相关部件设计技术的理解。 试验平台：MaxPlusII -through the use of VHDL hardware description language said a special components (such as interrupt controllers, error control coding / decoding devices, such as decoder) code analysis, building its logical structure, deepen the relevant parts design technology understanding. Test Platform : MaxPlusII
Platform: | Size: 30156 | Author: johnmad | Hits:

[Other resource] clock_time

Description: 本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
Platform: | Size: 1609 | Author: 阿兰 | Hits:

[Other resource] 4x4的数据选择器

Description: 用vhdl的4x4的数据选择器，在maxplusII下编译、仿真通过。是构成大型数字电路的重要部件。适合vhdl初学者分析学习。-4x4 with the VHDL data selectors, under the maxplusII compiler, simulation through. Yes constitute large-scale digital circuits important components. VHDL Analysis for beginners to learn.
Platform: | Size: 3394 | Author: roya | Hits:

[Other resource] vhd

Description: 基于maxplusII的EDA设计，自动绕线机的设计源程序。-maxplusII Based on the EDA design, automatic winding machine design source.
Platform: | Size: 157223 | Author: weini | Hits:

[Other resource] clock_CPLD

Description: 采用MaxPlusII写的一个小时钟程序，也是供初学参考。呵呵。注///版主，开发环境里面没有MaxPlusII.-MaxPlusII used to write a small clock procedures, as well as reference for beginners. Ha ha. Note / / / moderator, development environment there's no MaxPlusII.
Platform: | Size: 812260 | Author: Backy | Hits:

[Other resource] ref-ualaw

Description: A率/u率 压缩与解压缩的IP核，。 # 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。-A rate / u rate compression and decompression of the IP core,. By AHDL # languages, and the Quartus II MaxplusII use, the source code encryption.
Platform: | Size: 119678 | Author: zhangkun | Hits:

[Crack Hack] 硬件求解平方根

Description: 硬件求解平方根源代码加密 (硬件求解平方根的，将license添加到原有的MaxplusII或QuartusII的license中就可以直接使用，但源代码加密。altera提供 )-solving square root of the hardware encryption code (square root of the hardware solution will be added to the original license MaxplusII or Quartus II of the license which can be directly used, but the source code encryption. ALTERA provide)
Platform: | Size: 40676 | Author: 咱航 | Hits:

[Other resource] Parall_transfer_seior

Description: 此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function.
Platform: | Size: 1677 | Author: 郭春吉 | Hits:

[Windows Develop] cpu-maxplus

Description: MaxplusII编写的简易cpu，可实现简单加减法等操作-MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc
Platform: | Size: 513418 | Author: godtroop | Hits:

[Other] MaxPlusII

Description: Designing with MAX+PLUS
Platform: | Size: 905503 | Author: 陈宏 | Hits:

[Other resource] srbjq

Description: quartus环境下开发的三人表决器（三种不同的描述方式）maxplusII兼容
Platform: | Size: 1194 | Author: garychan | Hits:

[Other resource] USB20CTest_CpldCode

Description: maxplusII开发平台，适用于不是很熟悉USB上层开发的技术人员，可以快速开发出高速USB的DMA传输
Platform: | Size: 130506 | Author: 洪炉 | Hits:

[Com Port] 串行通讯的实现（附source code)maxplusII做的

Description: 串行通讯的实现（附source code)maxplusII做的-Serial Communication for the (source code) do maxplusII
Platform: | Size: 48867 | Author: 陈平 | Hits:

[Com Port] 串行通讯的实现（附source code)maxplusII做的

Description: 串行通讯的实现（附source code)maxplusII做的-Serial Communication for the (source code) do maxplusII
Platform: | Size: 48128 | Author: 陈平 | Hits:

[VHDL-FPGA-Verilog] MaxplusII123

Description: MaxplusII（中文）快速入门，对学习cpld或者FPGA的有帮助-MaxplusII (Chinese) Quick Start, the CPLD or FPGA-learning has helped
Platform: | Size: 262144 | Author: 柱陈 | Hits:

[VHDL-FPGA-Verilog] MAXPLUSII

Description: MAX+PLUSII使用说明 很具体是初学者的必读之物-MAX+ PLUSII use are very specific reading of material for beginners
Platform: | Size: 15360 | Author: 刘霁阳 | Hits:

[Other] MAXplusII

Description: CPLD数字电路设计--使用MAX+plusⅡ入门篇,学习MAX+plusII必备书籍。-CPLD digital circuit design- the use of MAX+ plus Ⅱ entry papers, study books MAX+ plusII necessary.
Platform: | Size: 20413440 | Author: 王海 | Hits:

[VHDL-FPGA-Verilog] MaxplusII

Description: 本电子书详细地介绍了VHDL语言开发环境 Max+plus II 软件的使用方法，让新手很快学会如何使用本软件-This book describes in detail VHDL language development environment Max+ plus II software to use, so that novices will soon learn how to use the software
Platform: | Size: 1048576 | Author: may | Hits:

[VHDL-FPGA-Verilog] shouhuoji

Description: 自动售货机，投币自动售货 MaxplusII下运行-Vending machines, coin-operated automatic vending MaxplusII run
Platform: | Size: 2048 | Author: 罗利娜 | Hits:
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